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//! I2C
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use crate :: gpio:: * ;
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use crate :: i2c:: config:: Config ;
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- use crate :: i2c:: { Error , I2c , I2cDirection , I2cExt , SCLPin , SDAPin } ;
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+ use crate :: i2c:: { self , Error , I2c , I2cDirection , I2cExt , SCLPin , SDAPin } ;
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use crate :: rcc:: * ;
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use crate :: stm32:: { I2C1 , I2C2 } ;
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use hal:: blocking:: i2c:: { Read , Write , WriteRead } ;
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pub trait I2cSlave {
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- /// Enable/ disable sbc . Default sbc is switched on.
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+ /// Enable/Disable Slave Byte Control . Default SBC is switched on.
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/// For master write/read the transaction should start with sbc disabled.
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- /// So ACK will be send on the last received byte. Then before the send phase sbc should enabled again
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+ /// So ACK will be send on the last received byte.
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+ /// Before the send phase SBC should be enabled again.
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fn slave_sbc ( & mut self , sbc_enabled : bool ) ;
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+ /// An optional tuple is returned with the address as sent by the master. The address is for 7 bit in range of 0..127
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+ fn slave_addressed ( & mut self ) -> Result < Option < ( u16 , I2cDirection ) > , Error > ;
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+
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/// Wait until this slave is addressed by the master.
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/// A tuple is returned with the address as sent by the master. The address is for 7 bit in range of 0..127
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fn slave_wait_addressed ( & mut self ) -> Result < ( u16 , I2cDirection ) , Error > ;
@@ -75,7 +79,7 @@ macro_rules! busy_wait {
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// This condition Will only happen when reload == 1 and sbr == 1 (slave) and nbytes was written.
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// Send a NACK, set nbytes to clear tcr flag
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$i2c. cr2. modify( |_, w| unsafe {
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- w. nack( ) . set_bit( ) . nbytes( ) . bits( 1 as u8 )
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+ w. nack( ) . set_bit( ) . nbytes( ) . bits( 1 as u8 )
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} ) ;
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// Make one extra loop here to wait on the stop condition
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} else if isr. addr( ) . bit_is_set( ) {
@@ -198,7 +202,7 @@ macro_rules! i2c {
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. oa2en( ) . set_bit( )
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} ) ;
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// Enable acknowlidge control
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- i2c. cr1. modify( |_, w| w. sbc( ) . set_bit( ) ) ;
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+ i2c. cr1. modify( |_, w| w. sbc( ) . set_bit( ) ) ;
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}
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// Enable pins
@@ -208,6 +212,27 @@ macro_rules! i2c {
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I2c { i2c, sda, scl }
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}
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+ pub fn listen( & mut self , ev: i2c:: Event ) {
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+ match ev {
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+ i2c:: Event :: AddressMatch => self . i2c. cr1. modify( |_, w| w. addrie( ) . set_bit( ) ) ,
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+ i2c:: Event :: Rxne => self . i2c. cr1. modify( |_, w| w. rxie( ) . set_bit( ) ) ,
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+ }
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+ }
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+
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+ pub fn unlisten( & mut self , ev: i2c:: Event ) {
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+ match ev {
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+ i2c:: Event :: AddressMatch => self . i2c. cr1. modify( |_, w| w. addrie( ) . clear_bit( ) ) ,
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+ i2c:: Event :: Rxne => self . i2c. cr1. modify( |_, w| w. rxie( ) . clear_bit( ) ) ,
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+ }
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+ }
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+
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+ pub fn clear_irq( & mut self , ev: i2c:: Event ) {
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+ match ev {
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+ i2c:: Event :: AddressMatch => self . i2c. icr. write( |w| w. addrcf( ) . set_bit( ) ) ,
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+ _ => { } ,
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+ }
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+ }
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+
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pub fn release( self ) -> ( $I2CX, SDA , SCL ) {
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( self . i2c, self . sda. release( ) , self . scl. release( ) )
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}
@@ -384,29 +409,36 @@ macro_rules! i2c {
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impl <SDA , SCL > I2cSlave for I2c <$I2CX, SDA , SCL > {
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fn slave_sbc( & mut self , sbc_enabled: bool ) {
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- // enable acknowlidge control
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+ // Enable Slave byte control
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self . i2c. cr1. modify( |_, w| w. sbc( ) . bit( sbc_enabled) ) ;
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}
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+ fn slave_addressed( & mut self ) -> Result <Option <( u16 , I2cDirection ) >, Error > {
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+ if self . i2c. isr. read( ) . addr( ) . bit_is_set( ) {
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+ let isr = self . i2c. isr. read( ) ;
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+ let current_address = isr. addcode( ) . bits( ) as u16 ;
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- fn slave_wait_addressed( & mut self ) -> Result <( u16 , I2cDirection ) , Error >{
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- // blocking wait until addressed
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- while self . i2c. isr. read( ) . addr( ) . bit_is_clear( ) { } ;
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-
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-
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- let isr = self . i2c. isr. read( ) ;
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- let current_address = isr. addcode( ) . bits( ) as u16 ;
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-
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- // if the dir bit is set it is a master write slave read operation
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- let direction = if isr. dir( ) . bit_is_set( )
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- {
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+ // if the dir bit is set it is a master write slave read operation
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+ let direction = if isr. dir( ) . bit_is_set( ) {
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I2cDirection :: MasterReadSlaveWrite
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} else {
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I2cDirection :: MasterWriteSlaveRead
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} ;
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- // do not yet release the clock stretching here.
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- // In the slave read function the nbytes is send, for this the addr bit must be set
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- Ok ( ( current_address, direction) )
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+ // do not yet release the clock stretching here.
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+ // In the slave read function the nbytes is send, for this the addr bit must be set
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+ Ok ( Some ( ( current_address, direction) ) )
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+
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+ } else {
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+ Ok ( None )
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+ }
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+ }
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+
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+ fn slave_wait_addressed( & mut self ) -> Result <( u16 , I2cDirection ) , Error > {
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+ loop {
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+ if let Some ( res) = self . slave_addressed( ) ? {
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+ return Ok ( res)
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+ }
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+ }
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}
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fn slave_write( & mut self , bytes: & [ u8 ] ) -> Result <( ) , Error > {
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