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Update for new pac stm32-rs/stm32-rs#1074 
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+36
-36
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5 files changed

+36
-36
lines changed

‎Cargo.toml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ version = "0.0.2"
1313

1414
[dependencies]
1515
nb = "0.1.1"
16-
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
17-
stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
16+
stm32g4 = { path = "../stm32-rs/stm32g4" } #git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
17+
#stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
1818
paste = "1.0"
1919
bitflags = "1.2"
2020
vcell = "0.1"

‎src/adc.rs‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1663,14 +1663,14 @@ macro_rules! adc {
16631663
self.calibrate_all();
16641664
self.apply_config(self.config);
16651665

1666-
self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
1666+
self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
16671667
self.adc_reg.cr().modify(|_, w| w.aden().set_bit());
16681668

16691669
// Wait for adc to get ready
16701670
while !self.adc_reg.isr().read().adrdy().bit_is_set() {}
16711671

16721672
// Clear ready flag
1673-
self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
1673+
self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
16741674

16751675
self.clear_end_of_conversion_flag();
16761676
}
@@ -1841,25 +1841,25 @@ macro_rules! adc {
18411841
self.config.difsel = df;
18421842

18431843
self.adc_reg.difsel().modify(|_, w| {w
1844-
.difsel_0().bit(df.get_channel(0).into() )
1845-
.difsel_1().bit(df.get_channel(1).into() )
1846-
.difsel_2().bit(df.get_channel(2).into() )
1847-
.difsel_3().bit(df.get_channel(3).into() )
1848-
.difsel_4().bit(df.get_channel(4).into() )
1849-
.difsel_5().bit(df.get_channel(5).into() )
1850-
.difsel_6().bit(df.get_channel(6).into() )
1851-
.difsel_7().bit(df.get_channel(7).into() )
1852-
.difsel_8().bit(df.get_channel(8).into() )
1853-
.difsel_9().bit(df.get_channel(9).into() )
1854-
.difsel_10().bit(df.get_channel(10).into() )
1855-
.difsel_11().bit(df.get_channel(11).into() )
1856-
.difsel_12().bit(df.get_channel(12).into() )
1857-
.difsel_13().bit(df.get_channel(13).into() )
1858-
.difsel_14().bit(df.get_channel(14).into() )
1859-
.difsel_15().bit(df.get_channel(15).into() )
1860-
.difsel_16().bit(df.get_channel(16).into() )
1861-
.difsel_17().bit(df.get_channel(17).into() )
1862-
.difsel_18().bit(df.get_channel(18).into() )
1844+
.difsel0().bit(df.get_channel(0).into() )
1845+
.difsel1().bit(df.get_channel(1).into() )
1846+
.difsel2().bit(df.get_channel(2).into() )
1847+
.difsel3().bit(df.get_channel(3).into() )
1848+
.difsel4().bit(df.get_channel(4).into() )
1849+
.difsel5().bit(df.get_channel(5).into() )
1850+
.difsel6().bit(df.get_channel(6).into() )
1851+
.difsel7().bit(df.get_channel(7).into() )
1852+
.difsel8().bit(df.get_channel(8).into() )
1853+
.difsel9().bit(df.get_channel(9).into() )
1854+
.difsel10().bit(df.get_channel(10).into() )
1855+
.difsel11().bit(df.get_channel(11).into() )
1856+
.difsel12().bit(df.get_channel(12).into() )
1857+
.difsel13().bit(df.get_channel(13).into() )
1858+
.difsel14().bit(df.get_channel(14).into() )
1859+
.difsel15().bit(df.get_channel(15).into() )
1860+
.difsel16().bit(df.get_channel(16).into() )
1861+
.difsel17().bit(df.get_channel(17).into() )
1862+
.difsel18().bit(df.get_channel(18).into() )
18631863
});
18641864
}
18651865

@@ -2015,7 +2015,7 @@ macro_rules! adc {
20152015
/// Resets the end-of-conversion flag
20162016
#[inline(always)]
20172017
pub fn clear_end_of_conversion_flag(&mut self) {
2018-
self.adc_reg.isr().modify(|_, w| w.eoc().set_bit());
2018+
self.adc_reg.isr().modify(|_, w| w.eoc().clear());
20192019
}
20202020

20212021
/// Block until the conversion is completed and return to configured
@@ -2124,7 +2124,7 @@ macro_rules! adc {
21242124
/// Resets the overrun flag
21252125
#[inline(always)]
21262126
pub fn clear_overrun_flag(&mut self) {
2127-
self.adc_reg.isr().modify(|_, w| w.ovr().set_bit());
2127+
self.adc_reg.isr().modify(|_, w| w.ovr().clear());
21282128
}
21292129
}
21302130

‎src/dma/channel.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -91,9 +91,9 @@ pub trait DMAExt<I> {
9191
impl DMAExt<Self> for DMA1 {
9292
fn split(self, rcc: &Rcc) -> Channels<DMA1> {
9393
// Enable DMAMux is not yet enabled
94-
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
94+
if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
9595
// Enable peripheral
96-
rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
96+
rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
9797
}
9898

9999
// Enable peripheral
@@ -106,9 +106,9 @@ impl DMAExt<Self> for DMA1 {
106106
impl DMAExt<Self> for DMA2 {
107107
fn split(self, rcc: &Rcc) -> Channels<DMA2> {
108108
// Enable DMAMux is not yet enabled
109-
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
109+
if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
110110
// Enable peripheral
111-
rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
111+
rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
112112
}
113113

114114
// Enable peripheral

‎src/pwr.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -103,10 +103,10 @@ pub(crate) fn current_vos() -> VoltageScale {
103103
// NOTE(unsafe): Read-only access
104104
let pwr = unsafe { &*PWR::ptr() };
105105

106-
match pwr.cr1().read().vos().bits() {
106+
match pwr.pwr_cr1().read().vos().bits() {
107107
0b00 => unreachable!(),
108108
0b01 => VoltageScale::Range1 {
109-
enable_boost: pwr.cr5().read().r1mode().bit(),
109+
enable_boost: pwr.pwr_cr5().read().r1mode().bit(),
110110
},
111111
0b10 => VoltageScale::Range2,
112112
0b11 => unreachable!(),
@@ -129,10 +129,10 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) {
129129
VoltageScale::Range1 { .. } => 0b01,
130130
VoltageScale::Range2 => 0b10,
131131
};
132-
pwr.cr1().modify(|_r, w| w.vos().bits(vos));
132+
pwr.pwr_cr1().modify(|_r, w| w.vos().bits(vos));
133133

134134
// Wait for ready
135-
while pwr.sr2().read().vosf().bit() {}
135+
while pwr.pwr_sr2().read().vosf().bit() {}
136136
}
137137

138138
/// Set new voltage scale
@@ -143,5 +143,5 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) {
143143
pub(crate) unsafe fn set_boost(enable_boost: bool) {
144144
let pwr = unsafe { &*PWR::ptr() };
145145
let r1mode = !enable_boost;
146-
pwr.cr5().modify(|_r, w| w.r1mode().bit(r1mode));
146+
pwr.pwr_cr5().modify(|_r, w| w.r1mode().bit(r1mode));
147147
}

‎src/rcc/mod.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -240,7 +240,7 @@ impl Rcc {
240240
pub fn unlock_rtc(&mut self) {
241241
self.rb.apb1enr1().modify(|_, w| w.pwren().set_bit());
242242
let pwr = unsafe { &(*PWR::ptr()) };
243-
pwr.cr1().modify(|_, w| w.dbp().set_bit());
243+
pwr.pwr_cr1().modify(|_, w| w.dbp().set_bit());
244244
}
245245

246246
fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks {
@@ -455,7 +455,7 @@ impl Rcc {
455455
let csr = self.rb.csr().read();
456456

457457
ResetReason {
458-
low_power: csr.lpwrstf().bit(),
458+
low_power: csr.lpwrrstf().bit(),
459459
window_watchdog: csr.wwdgrstf().bit(),
460460
independent_watchdog: csr.iwdgrstf().bit(),
461461
software: csr.sftrstf().bit(),

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