@@ -7,13 +7,12 @@ extern crate cortex_m_rt as rt;
77
88use core:: fmt:: Write ;
99
10+ use embedded_io:: { Read , ReadReady } ;
1011use hal:: prelude:: * ;
1112use hal:: pwr:: PwrExt ;
1213use hal:: serial:: * ;
1314use hal:: { rcc, stm32} ;
1415use stm32g4xx_hal as hal;
15- // TODO: switch to embedded-hal-nb
16- use hal:: hal_02:: serial:: Read ;
1716
1817use cortex_m_rt:: entry;
1918
@@ -52,23 +51,24 @@ fn main() -> ! {
5251
5352 let ( mut tx1, mut rx1) = usart. split ( ) ;
5453
54+ let mut buffer = [ 0 ; 4 ] ;
5555 let mut cnt = 0 ;
5656 loop {
5757 if rx1. fifo_threshold_reached ( ) {
5858 loop {
59- match rx1. read ( ) {
60- Err ( nb:: Error :: WouldBlock ) => {
61- // no more data available in fifo
62- break ;
63- }
64- Err ( nb:: Error :: Other ( _err) ) => {
59+ match rx1. read_ready ( ) {
60+ Ok ( true ) => ( ) ,
61+ Ok ( false ) => break , // no more data available in fifo
62+ Err ( e) => {
6563 // Handle other error Overrun, Framing, Noise or Parity
66- }
67- Ok ( byte) => {
68- writeln ! ( tx1, "{}: {}\r " , cnt, byte) . unwrap ( ) ;
69- cnt += 1 ;
64+ utils:: logger:: error!( "Error: {:?}" , e) ;
7065 }
7166 }
67+
68+ let count = rx1. read ( & mut buffer) . unwrap ( ) ;
69+ let bytes = & buffer[ count] ;
70+ writeln ! ( tx1, "{}: {}\r " , cnt, bytes) . unwrap ( ) ;
71+ cnt += count;
7272 }
7373 }
7474 }
0 commit comments