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usbalbinusbalbin
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Update for new pac with write and modify not returning unit type
1 parent 8286455 commit 369754d

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8 files changed

+22
-21
lines changed

8 files changed

+22
-21
lines changed

‎Cargo.toml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,8 @@ version = "0.0.2"
1313

1414
[dependencies]
1515
nb = "0.1.1"
16-
stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
16+
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
17+
stm32g4 = { version = "0.17.0", package = "stm32g4-staging" }
1718
paste = "1.0"
1819
bitflags = "1.2"
1920
vcell = "0.1"

‎src/adc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1947,7 +1947,7 @@ macro_rules! adc {
19471947
config::Sequence::Fourteen => self.adc_reg.sqr3().modify(|_, w| unsafe {w.sq14().bits(channel) }),
19481948
config::Sequence::Fifteen => self.adc_reg.sqr4().modify(|_, w| unsafe {w.sq15().bits(channel) }),
19491949
config::Sequence::Sixteen => self.adc_reg.sqr4().modify(|_, w| unsafe {w.sq16().bits(channel) }),
1950-
}
1950+
};
19511951

19521952
//Set the sample time for the channel
19531953
let st = u8::from(sample_time);
@@ -1973,7 +1973,7 @@ macro_rules! adc {
19731973
17 => self.adc_reg.smpr2().modify(|_, w| w.smp17().bits(st) ),
19741974
18 => self.adc_reg.smpr2().modify(|_, w| w.smp18().bits(st) ),
19751975
_ => unimplemented!(),
1976-
}
1976+
};
19771977
}
19781978
}
19791979
/// Synchronously convert a single sample

‎src/comparator.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -162,13 +162,13 @@ macro_rules! positive_input_pin {
162162
($COMP:ident, $pin_0:ident, $pin_1:ident) => {
163163
impl PositiveInput<$COMP> for &$pin_0<Analog> {
164164
fn setup(&self, comp: &$COMP) {
165-
comp.csr().modify(|_, w| w.inpsel().bit(false))
165+
comp.csr().modify(|_, w| w.inpsel().bit(false));
166166
}
167167
}
168168

169169
impl PositiveInput<$COMP> for &$pin_1<Analog> {
170170
fn setup(&self, comp: &$COMP) {
171-
comp.csr().modify(|_, w| w.inpsel().bit(true))
171+
comp.csr().modify(|_, w| w.inpsel().bit(true));
172172
}
173173
}
174174
};
@@ -213,7 +213,7 @@ macro_rules! negative_input_pin_helper {
213213
}
214214

215215
fn setup(&self, comp: &$COMP) {
216-
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) })
216+
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) });
217217
}
218218
}
219219
};
@@ -268,7 +268,7 @@ macro_rules! refint_input {
268268

269269
fn setup(&self, comp: &$COMP) {
270270
comp.csr()
271-
.modify(|_, w| unsafe { w.inmsel().bits(*self as u8) })
271+
.modify(|_, w| unsafe { w.inmsel().bits(*self as u8) });
272272
}
273273
}
274274
)+};
@@ -294,7 +294,7 @@ macro_rules! dac_input_helper {
294294
}
295295

296296
fn setup(&self, comp: &$COMP) {
297-
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) })
297+
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) });
298298
}
299299
}
300300
};

‎src/exti.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ impl ExtiExt for EXTI {
113113
line => self
114114
.imr2()
115115
.modify(|r, w| unsafe { w.bits(r.bits() | 1 << (line - 32)) }),
116-
}
116+
};
117117
}
118118

119119
fn unlisten(&self, ev: Event) {
@@ -133,7 +133,7 @@ impl ExtiExt for EXTI {
133133
line => {
134134
let mask = !(1 << (line - 32));
135135
self.imr2()
136-
.modify(|r, w| unsafe { w.bits(r.bits() & mask) })
136+
.modify(|r, w| unsafe { w.bits(r.bits() & mask) });
137137
}
138138
}
139139
}

‎src/gpio.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -488,7 +488,7 @@ macro_rules! gpio {
488488
unsafe {
489489
(*$GPIOX::ptr()).ospeedr().modify(|r, w| {
490490
w.bits((r.bits() & !(0b11 << offset)) | ((speed as u32) << offset))
491-
})
491+
});
492492
}
493493
self
494494
}

‎src/pwm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1259,7 +1259,7 @@ macro_rules! tim_hal {
12591259
2 => tim.cr1().modify(|_, w| unsafe { w.ckd().bits(1) }),
12601260
4 => tim.cr1().modify(|_, w| unsafe { w.ckd().bits(2) }),
12611261
_ => panic!("Should be unreachable, invalid deadtime prescaler"),
1262-
}
1262+
};
12631263

12641264
let bkp = match self.fault_polarity {
12651265
Polarity::ActiveLow => false,

‎src/rcc/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -362,7 +362,7 @@ impl Rcc {
362362
unsafe {
363363
// Adjust flash wait states
364364
let flash = &(*FLASH::ptr());
365-
flash.acr().modify(|_, w| w.latency().bits(latency))
365+
flash.acr().modify(|_, w| w.latency().bits(latency));
366366
}
367367
}
368368

‎src/serial/usart.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -529,8 +529,8 @@ macro_rules! uart_lp {
529529
Event::Rxne => self.tx.usart.cr1().modify(|_, w| w.rxneie().set_bit()),
530530
Event::Txe => self.tx.usart.cr1().modify(|_, w| w.txeie().set_bit()),
531531
Event::Idle => self.tx.usart.cr1().modify(|_, w| w.idleie().set_bit()),
532-
_ => {}
533-
}
532+
_ => unimplemented!(),
533+
};
534534
}
535535

536536
/// Stop listening for an interrupt event
@@ -539,8 +539,8 @@ macro_rules! uart_lp {
539539
Event::Rxne => self.tx.usart.cr1().modify(|_, w| w.rxneie().clear_bit()),
540540
Event::Txe => self.tx.usart.cr1().modify(|_, w| w.txeie().clear_bit()),
541541
Event::Idle => self.tx.usart.cr1().modify(|_, w| w.idleie().clear_bit()),
542-
_ => {}
543-
}
542+
_ => unimplemented!(),
543+
};
544544
}
545545

546546
/// Check if interrupt event is pending
@@ -683,8 +683,8 @@ macro_rules! uart_full {
683683
Event::Rxne => self.tx.usart.cr1().modify(|_, w| w.rxneie().set_bit()),
684684
Event::Txe => self.tx.usart.cr1().modify(|_, w| w.txeie().set_bit()),
685685
Event::Idle => self.tx.usart.cr1().modify(|_, w| w.idleie().set_bit()),
686-
_ => {}
687-
}
686+
_ => unimplemented!(),
687+
};
688688
}
689689

690690
/// Stop listening for an interrupt event
@@ -693,8 +693,8 @@ macro_rules! uart_full {
693693
Event::Rxne => self.tx.usart.cr1().modify(|_, w| w.rxneie().clear_bit()),
694694
Event::Txe => self.tx.usart.cr1().modify(|_, w| w.txeie().clear_bit()),
695695
Event::Idle => self.tx.usart.cr1().modify(|_, w| w.idleie().clear_bit()),
696-
_ => {}
697-
}
696+
_ => unimplemented!(),
697+
};
698698
}
699699

700700
/// Check if interrupt event is pending

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