Skip to content

Commit 3b12307

Browse files
usbalbinusbalbin
committed
Update DMA for new pac
1 parent c0f8396 commit 3b12307

File tree

1 file changed

+48
-48
lines changed

1 file changed

+48
-48
lines changed

‎src/dma/stream.rs

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ impl<I: Instance> StreamsTuple<I> {
182182
// the stream
183183
macro_rules! dma_stream {
184184
($(($name:ident, $number:expr,
185-
regs => $ccr:ident, $cparX:ident, $cmarX:ident, $cndtrX:ident,
185+
regs => $chX:ident,
186186
fields => $tcif:ident, $htif:ident, $teif:ident, $gif:ident, $tcisr:ident, $htisr:ident, $teisr:ident, $gisr:ident,
187187
dmamux => $dma1_cXcr:ident, $dma2_cXcr:ident, )
188188
),+$(,)*) => {
@@ -266,28 +266,28 @@ macro_rules! dma_stream {
266266
#[inline(always)]
267267
unsafe fn enable(&mut self) {
268268
//NOTE(unsafe) We only access the registers that belongs to the StreamX
269-
let dma = &*I::ptr();
270-
dma.$ccr.modify(|_, w| w.en().set_bit());
269+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
270+
dma_ch.cr.modify(|_, w| w.en().set_bit());
271271
}
272272

273273
#[inline(always)]
274274
fn is_enabled() -> bool {
275275
//NOTE(unsafe) Atomic read with no side effects
276-
let dma = unsafe { &*I::ptr() };
277-
dma.$ccr.read().en().bit_is_set()
276+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
277+
dma_ch.cr.read().en().bit_is_set()
278278
}
279279

280280
fn disable(&mut self) {
281281
if Self::is_enabled() {
282282
//NOTE(unsafe) We only access the registers that belongs to the StreamX
283-
let dma = unsafe { &*I::ptr() };
283+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
284284

285285
// Aborting an on-going transfer might cause interrupts to fire, disable
286286
// them
287287
let interrupts = Self::get_interrupts_enable();
288288
self.disable_interrupts();
289289

290-
dma.$ccr.modify(|_, w| w.en().clear_bit());
290+
dma_ch.cr.modify(|_, w| w.en().clear_bit());
291291
while Self::is_enabled() {}
292292

293293
self.clear_interrupts();
@@ -313,14 +313,14 @@ macro_rules! dma_stream {
313313
#[inline(always)]
314314
fn set_priority(&mut self, priority: config::Priority) {
315315
//NOTE(unsafe) We only access the registers that belongs to the StreamX
316-
let dma = unsafe { &*I::ptr() };
317-
dma.$ccr.modify(|_, w| unsafe { w.pl().bits(priority.bits()) });
316+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
317+
dma_ch.cr.modify(|_, w| unsafe { w.pl().bits(priority.bits()) });
318318
}
319319

320320
#[inline(always)]
321321
fn disable_interrupts(&mut self) {
322322
//NOTE(unsafe) We only access the registers that belongs to the StreamX
323-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
323+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
324324
dmacr.modify(|_, w| w
325325
.tcie().clear_bit()
326326
.teie().clear_bit()
@@ -332,8 +332,8 @@ macro_rules! dma_stream {
332332
#[inline(always)]
333333
fn enable_interrupts(&mut self, interrupt: Self::Interrupts) {
334334
//NOTE(unsafe) We only access the registers that belongs to the StreamX
335-
let dma = unsafe { &*I::ptr() };
336-
dma.$ccr.modify(|_, w| w
335+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
336+
dma_ch.cr.modify(|_, w| w
337337
.tcie().bit(interrupt.transfer_complete)
338338
.teie().bit(interrupt.transfer_error)
339339
.htie().bit(interrupt.half_transfer)
@@ -343,8 +343,8 @@ macro_rules! dma_stream {
343343
#[inline(always)]
344344
fn get_interrupts_enable() -> Self::Interrupts {
345345
//NOTE(unsafe) We only access the registers that belongs to the StreamX
346-
let dma = unsafe { &*I::ptr() };
347-
let cr = dma.$ccr.read();
346+
let dma_ch = unsafe { &*I::ptr() }.$chX();
347+
let cr = dma_ch.cr.read();
348348

349349
DmaInterrupts {
350350
transfer_complete: cr.tcie().bit_is_set(),
@@ -357,7 +357,7 @@ macro_rules! dma_stream {
357357
#[inline(always)]
358358
fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool) {
359359
//NOTE(unsafe) We only access the registers that belongs to the StreamX
360-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
360+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
361361
dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt));
362362
let _ = dmacr.read();
363363
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -366,7 +366,7 @@ macro_rules! dma_stream {
366366
#[inline(always)]
367367
fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool) {
368368
//NOTE(unsafe) We only access the registers that belongs to the StreamX
369-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
369+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
370370
dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt));
371371
let _ = dmacr.read();
372372
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -375,7 +375,7 @@ macro_rules! dma_stream {
375375
#[inline(always)]
376376
fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) {
377377
//NOTE(unsafe) We only access the registers that belongs to the StreamX
378-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
378+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
379379
dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt));
380380
let _ = dmacr.read();
381381
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -401,70 +401,70 @@ macro_rules! dma_stream {
401401
#[inline(always)]
402402
unsafe fn set_peripheral_address(&mut self, value: u32) {
403403
//NOTE(unsafe) We only access the registers that belongs to the StreamX
404-
let dma = &*I::ptr();
405-
dma.$cparX.write(|w| w.pa().bits(value));
404+
let dma_ch = unsafe { &*I::ptr() }.$chX();
405+
dma_ch.par.write(|w| w.pa().bits(value));
406406
}
407407

408408
#[inline(always)]
409409
unsafe fn set_memory_address(&mut self, value: u32) {
410410
//NOTE(unsafe) We only access the registers that belongs to the StreamX
411-
let dma = &*I::ptr();
412-
dma.$cmarX.write(|w| w.ma().bits(value) );
411+
let dma_ch = unsafe { &*I::ptr() }.$chX();
412+
dma_ch.mar.write(|w| w.ma().bits(value) );
413413
}
414414

415415
#[inline(always)]
416416
fn get_memory_address(&self) -> u32 {
417417
//NOTE(unsafe) We only access the registers that belongs to the StreamX
418-
let dma = unsafe { &*I::ptr() };
419-
dma.$cmarX.read().ma().bits()
418+
let dma_ch = unsafe { &*I::ptr() }.$chX();
419+
dma_ch.mar.read().ma().bits()
420420
}
421421

422422
#[inline(always)]
423423
fn set_number_of_transfers(&mut self, value: u16) {
424424
//NOTE(unsafe) We only access the registers that belongs to the StreamX
425-
let dma = unsafe { &*I::ptr() };
426-
dma.$cndtrX.write(|w| unsafe {w.ndt().bits(value) });
425+
let dma_ch = unsafe { &*I::ptr() }.$chX();
426+
dma_ch.ndtr.write(|w| unsafe {w.ndt().bits(value) });
427427
}
428428

429429
#[inline(always)]
430430
fn get_number_of_transfers() -> u16 {
431431
//NOTE(unsafe) We only access the registers that belongs to the StreamX
432-
let dma = unsafe { &*I::ptr() };
433-
dma.$cndtrX.read().ndt().bits()
432+
let dma_ch = unsafe { &*I::ptr() }.$chX();
433+
dma_ch.ndtr.read().ndt().bits()
434434
}
435435
#[inline(always)]
436436
unsafe fn set_memory_size(&mut self, size: u8) {
437437
//NOTE(unsafe) We only access the registers that belongs to the StreamX
438-
let dma = &*I::ptr();
439-
dma.$ccr.modify(|_, w| w.msize().bits(size));
438+
let dma_ch = unsafe { &*I::ptr() }.$chX();
439+
dma_ch.cr.modify(|_, w| w.msize().bits(size));
440440
}
441441

442442
#[inline(always)]
443443
unsafe fn set_peripheral_size(&mut self, size: u8) {
444444
//NOTE(unsafe) We only access the registers that belongs to the StreamX
445-
let dma = &*I::ptr();
446-
dma.$ccr.modify(|_, w| w.psize().bits(size));
445+
let dma_ch = unsafe { &*I::ptr() }.$chX();
446+
dma_ch.cr.modify(|_, w| w.psize().bits(size));
447447
}
448448

449449
#[inline(always)]
450450
fn set_memory_increment(&mut self, increment: bool) {
451451
//NOTE(unsafe) We only access the registers that belongs to the StreamX
452-
let dma = unsafe { &*I::ptr() };
453-
dma.$ccr.modify(|_, w| w.minc().bit(increment));
452+
let dma_ch = unsafe { &*I::ptr() }.$chX();
453+
dma_ch.cr.modify(|_, w| w.minc().bit(increment));
454454
}
455455

456456
#[inline(always)]
457457
fn set_peripheral_increment(&mut self, increment: bool) {
458458
//NOTE(unsafe) We only access the registers that belongs to the StreamX
459-
let dma = unsafe { &*I::ptr() };
460-
dma.$ccr.modify(|_, w| w.pinc().bit(increment));
459+
let dma_ch = unsafe { &*I::ptr() }.$chX();
460+
dma_ch.cr.modify(|_, w| w.pinc().bit(increment));
461461
}
462462

463463
#[inline(always)]
464464
fn set_direction(&mut self, direction: DmaDirection) {
465465
//NOTE(unsafe) We only access the registers that belongs to the StreamX
466-
let dma = unsafe { &*I::ptr() };
467-
dma.$ccr.modify(|_, w| {
466+
let dma_ch = unsafe { &*I::ptr() }.$chX();
467+
dma_ch.cr.modify(|_, w| {
468468
match direction {
469469
DmaDirection::PeripheralToMemory =>
470470
w.dir().clear_bit().mem2mem().clear_bit(),
@@ -479,8 +479,8 @@ macro_rules! dma_stream {
479479
#[inline(always)]
480480
fn set_circular_buffer(&mut self, circular_buffer: bool) {
481481
//NOTE(unsafe) We only access the registers that belongs to the StreamX
482-
let dma = unsafe { &*I::ptr() };
483-
dma.$ccr.modify(|_, w| w.circ().bit(circular_buffer));
482+
let dma_ch = unsafe { &*I::ptr() }.$chX();
483+
dma_ch.cr.modify(|_, w| w.circ().bit(circular_buffer));
484484
}
485485
}
486486

@@ -505,7 +505,7 @@ macro_rules! dma_stream {
505505
#[inline(always)]
506506
pub fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) {
507507
//NOTE(unsafe) We only access the registers that belongs to the StreamX
508-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
508+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
509509
dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt));
510510
let _ = dmacr.read();
511511
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -530,49 +530,49 @@ dma_stream!(
530530
// zero. May need updating if it gets fixed upstream.
531531
(
532532
Stream0, 0,
533-
regs => ccr1, cpar1, cmar1, cndtr1,
533+
regs => ch1,
534534
fields => tcif1, htif1, teif1, gif1, tcif1, htif1, teif1, gif1,
535535
dmamux => c0cr, c8cr,
536536
),
537537
(
538538
Stream1, 1,
539-
regs => ccr2, cpar2, cmar2, cndtr2,
539+
regs => ch2,
540540
fields => tcif2, htif2, teif2, gif2, tcif2, htif2, teif2, gif2,
541541
dmamux => c1cr, c9cr,
542542
),
543543
(
544544
Stream2, 2,
545-
regs => ccr3, cpar3, cmar3, cndtr3,
545+
regs => ch3,
546546
fields => tcif3, htif3, teif3, gif3, tcif3, htif3, teif3, gif3,
547547
dmamux => c2cr, c10cr,
548548
),
549549
(
550550
Stream3, 3,
551-
regs => ccr4, cpar4, cmar4, cndtr4,
551+
regs => ch4,
552552
fields => tcif4, htif4, teif4, gif4, tcif4, htif4, teif4, gif4,
553553
dmamux => c3cr, c11cr,
554554
),
555555
(
556556
Stream4, 4,
557-
regs => ccr5, cpar5, cmar5, cndtr5,
557+
regs => ch5,
558558
fields => tcif5, htif5, teif5, gif5, tcif5, htif5, teif5, gif5,
559559
dmamux => c4cr, c12cr,
560560
),
561561
(
562562
Stream5, 5,
563-
regs => ccr6, cpar6, cmar6, cndtr6,
563+
regs => ch6,
564564
fields => tcif6, htif6, teif6, gif6, tcif6, htif6, teif6, gif6,
565565
dmamux => c5cr, c13cr,
566566
),
567567
(
568568
Stream6, 6,
569-
regs => ccr7, cpar7, cmar7, cndtr7,
569+
regs => ch7,
570570
fields => tcif7, htif7, teif7, gif7, tcif7, htif7, teif7, gif7,
571571
dmamux => c6cr, c14cr,
572572
),
573573
(
574574
Stream7, 7,
575-
regs => ccr8, cpar8, cmar8, cndtr8,
575+
regs => ch8,
576576
fields => tcif8, htif8, teif8, gif8, tcif8, htif8, teif8, gif8,
577577
dmamux => c7cr, c15cr,
578578
),

0 commit comments

Comments
 (0)