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Update for new pac changes
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7 files changed

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-225
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7 files changed

+205
-225
lines changed

‎Cargo.toml‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,8 @@ version = "0.0.2"
1414
[dependencies]
1515
nb = "0.1.1"
1616
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
17-
stm32g4 = { version = "0.17.0", package = "stm32g4-staging" }
17+
#stm32g4 = { version = "0.18.0", package = "stm32g4-staging" }
18+
stm32g4 = { path = "../stm32-rs/stm32g4" }
1819
paste = "1.0"
1920
bitflags = "1.2"
2021
vcell = "0.1"

‎src/hrtim/capture.rs‎

Lines changed: 23 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,12 @@ pub fn dma_value_to_signed(x: u32, period: u16) -> i32 {
149149
}
150150

151151
macro_rules! impl_capture {
152-
($($TIMX:ident: $CH:ident, $cptXYr:ident, $cptXYcr:ident, $cptXx:ident, $dier:ident, $icr:ident, $isr:ident, $cptXie:ident, $cptXde:ident, $cptXc:ident, $cptX:ident, $mux:expr),+) => {$(
152+
($($TIMX:ident: $mux:expr),+) => {$(
153+
impl_capture!($TIMX: Ch1, cpt1r, cpt1cr, cpt1, cpt1ie, cpt1de, cpt1c, $mux);
154+
impl_capture!($TIMX: Ch2, cpt2r, cpt2cr, cpt2, cpt2ie, cpt2de, cpt2c, $mux);
155+
)+};
156+
157+
($TIMX:ident: $CH:ident, $cptXr:ident, $cptXcr:ident, $cptX:ident, $cptXie:ident, $cptXde:ident, $cptXc:ident, $mux:expr) => {
153158
impl<PSCL> HrCapt<$TIMX, PSCL, $CH, NoDma> {
154159
/// Add event to capture
155160
///
@@ -160,7 +165,7 @@ macro_rules! impl_capture {
160165

161166
// SAFETY: We are the only one with access to cptXYcr
162167
unsafe {
163-
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() | E::BITS));
168+
tim.$cptXcr().modify(|r, w| w.bits(r.bits() | E::BITS));
164169
}
165170
}
166171

@@ -170,7 +175,7 @@ macro_rules! impl_capture {
170175

171176
// SAFETY: We are the only one with access to cptXYcr
172177
unsafe {
173-
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
178+
tim.$cptXcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
174179
}
175180
}
176181

@@ -179,7 +184,7 @@ macro_rules! impl_capture {
179184
// SAFETY: We are the only one with access to cptXYcr
180185
let tim = unsafe { &*$TIMX::ptr() };
181186

182-
tim.$cptXYcr().modify(|_, w| w.swcpt().set_bit());
187+
tim.$cptXcr().modify(|_, w| w.swcpt().set_bit());
183188
}
184189

185190
// TODO: It would be sufficient to instead of hr_control only require exclusive access to the owning timer
@@ -188,13 +193,13 @@ macro_rules! impl_capture {
188193
pub fn enable_interrupt(&mut self, enable: bool, _hr_control: &mut super::HrPwmControl) {
189194
let tim = unsafe { &*$TIMX::ptr() };
190195

191-
tim.$dier().modify(|_r, w| w.$cptXie().bit(enable));
196+
tim.dier().modify(|_r, w| w.$cptXie().bit(enable));
192197
}
193198

194199
pub fn enable_dma(self, _ch: timer::DmaChannel<$TIMX>) -> HrCapt<$TIMX, PSCL, $CH, Dma> {
195200
// SAFETY: We own the only insance of this timers dma channel, no one else can do this
196201
let tim = unsafe { &*$TIMX::ptr() };
197-
tim.$dier().modify(|_r, w| w.$cptXde().set_bit());
202+
tim.dier().modify(|_r, w| w.$cptXde().set_bit());
198203
HrCapt {
199204
_x: PhantomData
200205
}
@@ -204,13 +209,13 @@ macro_rules! impl_capture {
204209
impl<PSCL, DMA> HrCapture for HrCapt<$TIMX, PSCL, $CH, DMA> {
205210
fn get_last(&self) -> (u16, CountingDirection) {
206211
let tim = unsafe { &*$TIMX::ptr() };
207-
let data = tim.$cptXYr().read();
212+
let data = tim.$cptXr().read();
208213

209214
let dir = match data.dir().bit() {
210215
true => CountingDirection::Down,
211216
false => CountingDirection::Up,
212217
};
213-
let value = data.$cptXx().bits();
218+
let value = data.cpt().bits();
214219

215220
(value, dir)
216221
}
@@ -219,47 +224,36 @@ macro_rules! impl_capture {
219224
let tim = unsafe { &*$TIMX::ptr() };
220225

221226
// No need for exclusive access since this is a write only register
222-
tim.$icr().write(|w| w.$cptXc().set_bit());
227+
tim.icr().write(|w| w.$cptXc().bit(true));
223228
}
224229

225230
fn is_pending(&self) -> bool {
226231
let tim = unsafe { &*$TIMX::ptr() };
227232

228233
// No need for exclusive access since this is a read only register
229-
tim.$isr().read().$cptX().bit()
234+
tim.isr().read().$cptX().bit()
230235
}
231236
}
232237

233238
unsafe impl<PSCL> TargetAddress<PeripheralToMemory> for HrCapt<$TIMX, PSCL, $CH, Dma> {
234239
#[inline(always)]
235240
fn address(&self) -> u32 {
236241
let tim = unsafe { &*$TIMX::ptr() };
237-
&tim.$cptXYr() as *const _ as u32
242+
&tim.$cptXr() as *const _ as u32
238243
}
239244

240245
type MemSize = u32;
241246

242247
const REQUEST_LINE: Option<u8> = Some($mux as u8);
243248
}
244-
)+};
249+
};
245250
}
246251

247252
impl_capture! {
248-
HRTIM_TIMA: Ch1, cpt1ar, cpt1acr, cpt1x, timadier, timaicr, timaisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMA,
249-
HRTIM_TIMA: Ch2, cpt2ar, cpt2acr, cpt2x, timadier, timaicr, timaisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMA,
250-
251-
HRTIM_TIMB: Ch1, cpt1br, cpt1bcr, cpt1x, timbdier, timbicr, timbisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMB,
252-
HRTIM_TIMB: Ch2, cpt2br, cpt2bcr, cpt2x, timbdier, timbicr, timbisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMB,
253-
254-
HRTIM_TIMC: Ch1, cpt1cr, cpt1ccr, cpt1x, timcdier, timcicr, timcisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMC,
255-
HRTIM_TIMC: Ch2, cpt2cr, cpt2ccr, cpt2x, timcdier, timcicr, timcisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMC,
256-
257-
HRTIM_TIMD: Ch1, cpt1dr, cpt1dcr, cpt1x, timddier, timdicr, timdisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMD,
258-
HRTIM_TIMD: Ch2, cpt2dr, cpt2dcr, cpt2x, timddier, timdicr, timdisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMD,
259-
260-
HRTIM_TIME: Ch1, cpt1er, cpt1ecr, cpt1x, timedier, timeicr, timeisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIME,
261-
HRTIM_TIME: Ch2, cpt2er, cpt2ecr, cpt2x, timedier, timeicr, timeisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIME,
262-
263-
HRTIM_TIMF: Ch1, cpt1fr, cpt1fcr, cpt1x, timfdier, timficr, timfisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMF,
264-
HRTIM_TIMF: Ch2, cpt2fr, cpt2fcr, cpt2x, timfdier, timficr, timfisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMF
253+
HRTIM_TIMA: DmaMuxResources::HRTIM_TIMA,
254+
HRTIM_TIMB: DmaMuxResources::HRTIM_TIMB,
255+
HRTIM_TIMC: DmaMuxResources::HRTIM_TIMC,
256+
HRTIM_TIMD: DmaMuxResources::HRTIM_TIMD,
257+
HRTIM_TIME: DmaMuxResources::HRTIM_TIME,
258+
HRTIM_TIMF: DmaMuxResources::HRTIM_TIMF
265259
}

‎src/hrtim/compare_register.rs‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -21,17 +21,17 @@ use super::adc_trigger::Adc6810Trigger as Adc6810;
2121

2222
macro_rules! hrtim_cr_helper {
2323
(HRTIM_MASTER: $cr_type:ident:
24-
$cmpXYr:ident, $cmpYx:ident,
24+
$cmpXYr:ident,
2525
[$(($Trigger:ty: $trigger_bits:expr)),*],
2626
[$(($event_dst:ident, $tim_event_index:expr)),*],
2727
$bit_index:literal
2828
) => {
2929
// Strip bit_index since master timer has other bits that are common across all destinations
30-
hrtim_cr_helper!(HRTIM_MASTER: $cr_type: $cmpXYr, $cmpYx, [$(($Trigger: $trigger_bits)),*], [$(($event_dst, $tim_event_index)),*]);
30+
hrtim_cr_helper!(HRTIM_MASTER: $cr_type: $cmpXYr, [$(($Trigger: $trigger_bits)),*], [$(($event_dst, $tim_event_index)),*]);
3131
};
3232

3333
($TIMX:ident: $cr_type:ident:
34-
$cmpXYr:ident, $cmpYx:ident,
34+
$cmpXYr:ident,
3535
[$(($Trigger:ty: $trigger_bits:expr)),*],
3636
[$(($event_dst:ident, $tim_event_index:expr)),*]
3737
$(, $bit_index:literal)*
@@ -40,12 +40,12 @@ macro_rules! hrtim_cr_helper {
4040
fn get_duty(&self) -> u16 {
4141
let tim = unsafe { &*$TIMX::ptr() };
4242

43-
tim.$cmpXYr().read().$cmpYx().bits()
43+
tim.$cmpXYr().read().cmp().bits()
4444
}
4545
fn set_duty(&mut self, duty: u16) {
4646
let tim = unsafe { &*$TIMX::ptr() };
4747

48-
tim.$cmpXYr().write(|w| unsafe { w.$cmpYx().bits(duty) });
48+
tim.$cmpXYr().write(|w| unsafe { w.cmp().bits(duty) });
4949
}
5050
}
5151

@@ -73,67 +73,67 @@ macro_rules! hrtim_cr_helper {
7373

7474
macro_rules! hrtim_cr {
7575
($($TIMX:ident: [
76-
[$cmpX1r:ident, $cmp1x:ident, [$(($cr1_trigger:ident: $cr1_trigger_bits:expr)),*], [$(($cr1_event_dst:ident, $cr1_tim_event_index:expr)),*]],
77-
[$cmpX2r:ident, $cmp2x:ident, [$(($cr2_trigger:ident: $cr2_trigger_bits:expr)),*], [$(($cr2_event_dst:ident, $cr2_tim_event_index:expr)),*]],
78-
[$cmpX3r:ident, $cmp3x:ident, [$(($cr3_trigger:ident: $cr3_trigger_bits:expr)),*], [$(($cr3_event_dst:ident, $cr3_tim_event_index:expr)),*]],
79-
[$cmpX4r:ident, $cmp4x:ident, [$(($cr4_trigger:ident: $cr4_trigger_bits:expr)),*], [$(($cr4_event_dst:ident, $cr4_tim_event_index:expr)),*]]
76+
[$(($cr1_trigger:ident: $cr1_trigger_bits:expr)),*], [$(($cr1_event_dst:ident, $cr1_tim_event_index:expr)),*],
77+
[$(($cr2_trigger:ident: $cr2_trigger_bits:expr)),*], [$(($cr2_event_dst:ident, $cr2_tim_event_index:expr)),*],
78+
[$(($cr3_trigger:ident: $cr3_trigger_bits:expr)),*], [$(($cr3_event_dst:ident, $cr3_tim_event_index:expr)),*],
79+
[$(($cr4_trigger:ident: $cr4_trigger_bits:expr)),*], [$(($cr4_event_dst:ident, $cr4_tim_event_index:expr)),*]
8080
]),+) => {$(
81-
hrtim_cr_helper!($TIMX: HrCr1: $cmpX1r, $cmp1x, [$(($cr1_trigger: $cr1_trigger_bits)),*], [$(($cr1_event_dst, $cr1_tim_event_index)),*], 3);
82-
hrtim_cr_helper!($TIMX: HrCr2: $cmpX2r, $cmp2x, [$(($cr2_trigger: $cr2_trigger_bits)),*], [$(($cr2_event_dst, $cr2_tim_event_index)),*], 4);
83-
hrtim_cr_helper!($TIMX: HrCr3: $cmpX3r, $cmp3x, [$(($cr3_trigger: $cr3_trigger_bits)),*], [$(($cr3_event_dst, $cr3_tim_event_index)),*], 5);
84-
hrtim_cr_helper!($TIMX: HrCr4: $cmpX4r, $cmp4x, [$(($cr4_trigger: $cr4_trigger_bits)),*], [$(($cr4_event_dst, $cr4_tim_event_index)),*], 6);
81+
hrtim_cr_helper!($TIMX: HrCr1: cmp1r, [$(($cr1_trigger: $cr1_trigger_bits)),*], [$(($cr1_event_dst, $cr1_tim_event_index)),*], 3);
82+
hrtim_cr_helper!($TIMX: HrCr2: cmp2r, [$(($cr2_trigger: $cr2_trigger_bits)),*], [$(($cr2_event_dst, $cr2_tim_event_index)),*], 4);
83+
hrtim_cr_helper!($TIMX: HrCr3: cmp3r, [$(($cr3_trigger: $cr3_trigger_bits)),*], [$(($cr3_event_dst, $cr3_tim_event_index)),*], 5);
84+
hrtim_cr_helper!($TIMX: HrCr4: cmp4r, [$(($cr4_trigger: $cr4_trigger_bits)),*], [$(($cr4_event_dst, $cr4_tim_event_index)),*], 6);
8585
)+};
8686
}
8787

8888
// See RM0440 Table 218. 'Events mapping across timer A to F'
8989
hrtim_cr! {
9090
HRTIM_MASTER: [
91-
[mcmp1r, mcmp1, [(Adc13: 1 << 0), (Adc24: 1 << 0), (Adc579: 0), (Adc6810: 0) ], []],
92-
[mcmp2r, mcmp2, [(Adc13: 1 << 1), (Adc24: 1 << 1), (Adc579: 1), (Adc6810: 1) ], []],
93-
[mcmp3r, mcmp3, [(Adc13: 1 << 2), (Adc24: 1 << 2), (Adc579: 2), (Adc6810: 2) ], []],
94-
[mcmp4r, mcmp4, [(Adc13: 1 << 3), (Adc24: 1 << 3), (Adc579: 3), (Adc6810: 3) ], []]
91+
[(Adc13: 1 << 0), (Adc24: 1 << 0), (Adc579: 0), (Adc6810: 0) ], [],
92+
[(Adc13: 1 << 1), (Adc24: 1 << 1), (Adc579: 1), (Adc6810: 1) ], [],
93+
[(Adc13: 1 << 2), (Adc24: 1 << 2), (Adc579: 2), (Adc6810: 2) ], [],
94+
[(Adc13: 1 << 3), (Adc24: 1 << 3), (Adc579: 3), (Adc6810: 3) ], []
9595
],
9696

9797
HRTIM_TIMA: [
98-
[cmp1ar, cmp1x, [ ], [(HRTIM_TIMB, 1), (HRTIM_TIMD, 1) ]],
99-
[cmp2ar, cmp2x, [ (Adc24: 1 << 10), (Adc6810: 10)], [(HRTIM_TIMB, 2), (HRTIM_TIMC, 1) ]],
100-
[cmp3ar, cmp3x, [(Adc13: 1 << 11), (Adc579: 10) ], [(HRTIM_TIMC, 2), (HRTIM_TIMF, 1) ]],
101-
[cmp4ar, cmp4x, [(Adc13: 1 << 12), (Adc24: 1 << 12), (Adc579: 11), (Adc6810: 11)], [(HRTIM_TIMD, 2), (HRTIM_TIME, 1) ]]
98+
[ ], [(HRTIM_TIMB, 1), (HRTIM_TIMD, 1) ],
99+
[ (Adc24: 1 << 10), (Adc6810: 10)], [(HRTIM_TIMB, 2), (HRTIM_TIMC, 1) ],
100+
[(Adc13: 1 << 11), (Adc579: 10) ], [(HRTIM_TIMC, 2), (HRTIM_TIMF, 1) ],
101+
[(Adc13: 1 << 12), (Adc24: 1 << 12), (Adc579: 11), (Adc6810: 11)], [(HRTIM_TIMD, 2), (HRTIM_TIME, 1) ]
102102
],
103103

104104
HRTIM_TIMB: [
105-
[cmp1br, cmp1x, [ ], [(HRTIM_TIMA, 1), (HRTIM_TIMF, 2) ]],
106-
[cmp2br, cmp2x, [ (Adc24: 1 << 14), (Adc6810: 13)], [(HRTIM_TIMA, 2), (HRTIM_TIMC, 3), (HRTIM_TIMD, 3)]],
107-
[cmp3br, cmp3x, [(Adc13: 1 << 16), (Adc579: 14) ], [(HRTIM_TIMC, 4), (HRTIM_TIME, 2) ]],
108-
[cmp4br, cmp4x, [(Adc13: 1 << 17), (Adc24: 1 << 16), (Adc579: 15), (Adc6810: 14)], [(HRTIM_TIMD, 4), (HRTIM_TIME, 3), (HRTIM_TIMF, 3)]]
105+
[ ], [(HRTIM_TIMA, 1), (HRTIM_TIMF, 2) ],
106+
[ (Adc24: 1 << 14), (Adc6810: 13)], [(HRTIM_TIMA, 2), (HRTIM_TIMC, 3), (HRTIM_TIMD, 3)],
107+
[(Adc13: 1 << 16), (Adc579: 14) ], [(HRTIM_TIMC, 4), (HRTIM_TIME, 2) ],
108+
[(Adc13: 1 << 17), (Adc24: 1 << 16), (Adc579: 15), (Adc6810: 14)], [(HRTIM_TIMD, 4), (HRTIM_TIME, 3), (HRTIM_TIMF, 3)]
109109
],
110110

111111
HRTIM_TIMC: [
112-
[cmp1cr, cmp1x, [ ], [(HRTIM_TIME, 4), (HRTIM_TIMF, 4) ]],
113-
[cmp2cr, cmp2x, [ (Adc24: 1 << 18), (Adc6810: 16)], [(HRTIM_TIMA, 3), (HRTIM_TIME, 5) ]],
114-
[cmp3cr, cmp3x, [(Adc13: 1 << 21), (Adc579: 18) ], [(HRTIM_TIMA, 4), (HRTIM_TIMB, 3) ]],
115-
[cmp4cr, cmp4x, [(Adc13: 1 << 22), (Adc24: 1 << 20), (Adc579: 19), (Adc6810: 17)], [(HRTIM_TIMB, 4), (HRTIM_TIMD, 5), (HRTIM_TIMF, 5)]]
112+
[ ], [(HRTIM_TIME, 4), (HRTIM_TIMF, 4) ],
113+
[ (Adc24: 1 << 18), (Adc6810: 16)], [(HRTIM_TIMA, 3), (HRTIM_TIME, 5) ],
114+
[(Adc13: 1 << 21), (Adc579: 18) ], [(HRTIM_TIMA, 4), (HRTIM_TIMB, 3) ],
115+
[(Adc13: 1 << 22), (Adc24: 1 << 20), (Adc579: 19), (Adc6810: 17)], [(HRTIM_TIMB, 4), (HRTIM_TIMD, 5), (HRTIM_TIMF, 5)]
116116
],
117117

118118
HRTIM_TIMD: [
119-
[cmp1dr, cmp1x, [ ], [(HRTIM_TIMA, 5), (HRTIM_TIME, 6) ]],
120-
[cmp2dr, cmp2x, [ (Adc24: 1 << 23), (Adc6810: 20)], [(HRTIM_TIMA, 6), (HRTIM_TIMC, 5), (HRTIM_TIME, 7)]],
121-
[cmp3dr, cmp3x, [(Adc13: 1 << 25), (Adc579: 21) ], [(HRTIM_TIMB, 5), (HRTIM_TIMF, 6) ]],
122-
[cmp4dr, cmp4x, [(Adc13: 1 << 26), (Adc24: 1 << 25), (Adc579: 22), (Adc6810: 21)], [(HRTIM_TIMB, 6), (HRTIM_TIMC, 6), (HRTIM_TIMF, 7)]]
119+
[ ], [(HRTIM_TIMA, 5), (HRTIM_TIME, 6) ],
120+
[ (Adc24: 1 << 23), (Adc6810: 20)], [(HRTIM_TIMA, 6), (HRTIM_TIMC, 5), (HRTIM_TIME, 7)],
121+
[(Adc13: 1 << 25), (Adc579: 21) ], [(HRTIM_TIMB, 5), (HRTIM_TIMF, 6) ],
122+
[(Adc13: 1 << 26), (Adc24: 1 << 25), (Adc579: 22), (Adc6810: 21)], [(HRTIM_TIMB, 6), (HRTIM_TIMC, 6), (HRTIM_TIMF, 7)]
123123
],
124124

125125
HRTIM_TIME: [
126-
[cmp1er, cmp1x, [ ], [(HRTIM_TIMB, 7), (HRTIM_TIMD, 6) ]],
127-
[cmp2er, cmp2x, [ (Adc24: 1 << 28), (Adc6810: 24)], [(HRTIM_TIMB, 8), (HRTIM_TIMF, 8) ]],
128-
[cmp3er, cmp3x, [(Adc13: 1 << 29), (Adc24: 1 << 29), (Adc579: 24), (Adc6810: 25)], [(HRTIM_TIMA, 7), (HRTIM_TIMC, 7), (HRTIM_TIMF, 9)]],
129-
[cmp4er, cmp4x, [(Adc13: 1 << 30), (Adc24: 1 << 30), (Adc579: 25), (Adc6810: 26)], [(HRTIM_TIMA, 8), (HRTIM_TIMC, 8), (HRTIM_TIMD, 7)]]
126+
[ ], [(HRTIM_TIMB, 7), (HRTIM_TIMD, 6) ],
127+
[ (Adc24: 1 << 28), (Adc6810: 24)], [(HRTIM_TIMB, 8), (HRTIM_TIMF, 8) ],
128+
[(Adc13: 1 << 29), (Adc24: 1 << 29), (Adc579: 24), (Adc6810: 25)], [(HRTIM_TIMA, 7), (HRTIM_TIMC, 7), (HRTIM_TIMF, 9)],
129+
[(Adc13: 1 << 30), (Adc24: 1 << 30), (Adc579: 25), (Adc6810: 26)], [(HRTIM_TIMA, 8), (HRTIM_TIMC, 8), (HRTIM_TIMD, 7)]
130130
],
131131

132132
HRTIM_TIMF: [
133-
[cmp1fr, cmp1x, [ (Adc24: 1 << 15) ], [(HRTIM_TIMD, 8) ]],
134-
[cmp2fr, cmp2x, [(Adc13: 1 << 10), (Adc24: 1 << 11), (Adc579: 27), (Adc6810: 28)], [(HRTIM_TIMC, 9) ]],
135-
[cmp3fr, cmp3x, [(Adc13: 1 << 15), (Adc579: 28), (Adc6810: 29)], [(HRTIM_TIMB, 9), (HRTIM_TIMD, 9), (HRTIM_TIME, 8)]],
136-
[cmp4fr, cmp4x, [(Adc13: 1 << 20), (Adc24: 1 << 19), (Adc579: 29), (Adc6810: 30)], [(HRTIM_TIMA, 9), (HRTIM_TIME, 9) ]]
133+
[ (Adc24: 1 << 15) ], [(HRTIM_TIMD, 8) ],
134+
[(Adc13: 1 << 10), (Adc24: 1 << 11), (Adc579: 27), (Adc6810: 28)], [(HRTIM_TIMC, 9) ],
135+
[(Adc13: 1 << 15), (Adc579: 28), (Adc6810: 29)], [(HRTIM_TIMB, 9), (HRTIM_TIMD, 9), (HRTIM_TIME, 8)],
136+
[(Adc13: 1 << 20), (Adc24: 1 << 19), (Adc579: 29), (Adc6810: 30)], [(HRTIM_TIMA, 9), (HRTIM_TIME, 9) ]
137137
]
138138
}
139139

‎src/hrtim/fault.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -267,7 +267,7 @@ macro_rules! impl_flt_monitor {
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}
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impl_flt_monitor!(
270-
FltMonitorSys: (sysflt, sysfltc, sysflte),
270+
FltMonitorSys: (sysflt, sysfltc, sysfltie),
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FltMonitor1: (flt1, flt1c, flt1ie),
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FltMonitor2: (flt2, flt2c, flt2ie),
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FltMonitor3: (flt3, flt3c, flt3ie),

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