@@ -20,7 +20,22 @@ use super::adc_trigger::Adc579Trigger as Adc579;
2020use super :: adc_trigger:: Adc6810Trigger as Adc6810 ;
2121
2222macro_rules! hrtim_cr_helper {
23- ( $TIMX: ident: $cr_type: ident: $cmpXYr: ident, $cmpYx: ident, $( ( $Trigger: ty: $trigger_bits: expr) ) ,* ) => {
23+ ( HRTIM_MASTER : $cr_type: ident:
24+ $cmpXYr: ident, $cmpYx: ident,
25+ [ $( ( $Trigger: ty: $trigger_bits: expr) ) ,* ] ,
26+ [ $( ( $event_dst: ident, $tim_event_index: expr) ) ,* ] ,
27+ $bit_index: literal
28+ ) => {
29+ // Strip bit_index since master timer has other bits that are common across all destinations
30+ hrtim_cr_helper!( HRTIM_MASTER : $cr_type: $cmpXYr, $cmpYx, [ $( ( $Trigger: $trigger_bits) ) ,* ] , [ $( ( $event_dst, $tim_event_index) ) ,* ] ) ;
31+ } ;
32+
33+ ( $TIMX: ident: $cr_type: ident:
34+ $cmpXYr: ident, $cmpYx: ident,
35+ [ $( ( $Trigger: ty: $trigger_bits: expr) ) ,* ] ,
36+ [ $( ( $event_dst: ident, $tim_event_index: expr) ) ,* ]
37+ $( , $bit_index: literal) *
38+ ) => {
2439 impl <PSCL > HrCompareRegister for $cr_type<$TIMX, PSCL > {
2540 fn get_duty( & self ) -> u16 {
2641 let tim = unsafe { & * $TIMX:: ptr( ) } ;
@@ -34,73 +49,138 @@ macro_rules! hrtim_cr_helper {
3449 }
3550 }
3651
37- $( impl <PSCL > $Trigger for $cr_type<$TIMX, PSCL > {
38- const BITS : u32 = $trigger_bits;
39- } ) *
52+ $(
53+ /// Compare match event
54+ impl <PSCL > super :: event:: EventSource <$TIMX, PSCL > for $cr_type<$TIMX, PSCL > {
55+ const BITS : u32 = 1 << $bit_index;
56+ }
57+ ) *
58+
59+ $(
60+ /// Compare match event for neighbor timer
61+ impl <PSCL > super :: event:: EventSource <$event_dst, PSCL > for $cr_type<$TIMX, PSCL > {
62+ const BITS : u32 = 1 << ( $tim_event_index + 11 ) ; // TIMEVNT1 is at bit 12, TIMEVNT2 at bit 13 etc
63+ }
64+ ) *
65+
66+ $(
67+ impl <PSCL > $Trigger for $cr_type<$TIMX, PSCL > {
68+ const BITS : u32 = $trigger_bits;
69+ }
70+ ) *
4071 } ;
4172}
4273
4374macro_rules! hrtim_cr {
4475 ( $( $TIMX: ident: [
45- [ $cmpX1r: ident, $cmp1x: ident, $( ( $cr1_trigger: ident: $cr1_trigger_bits: expr) ) ,* ] ,
46- [ $cmpX2r: ident, $cmp2x: ident, $( ( $cr2_trigger: ident: $cr2_trigger_bits: expr) ) ,* ] ,
47- [ $cmpX3r: ident, $cmp3x: ident, $( ( $cr3_trigger: ident: $cr3_trigger_bits: expr) ) ,* ] ,
48- [ $cmpX4r: ident, $cmp4x: ident, $( ( $cr4_trigger: ident: $cr4_trigger_bits: expr) ) ,* ]
76+ [ $cmpX1r: ident, $cmp1x: ident, [ $( ( $cr1_trigger: ident: $cr1_trigger_bits: expr) ) ,* ] , [ $ ( ( $cr1_event_dst : ident , $cr1_tim_event_index : expr ) ) , * ] ] ,
77+ [ $cmpX2r: ident, $cmp2x: ident, [ $( ( $cr2_trigger: ident: $cr2_trigger_bits: expr) ) ,* ] , [ $ ( ( $cr2_event_dst : ident , $cr2_tim_event_index : expr ) ) , * ] ] ,
78+ [ $cmpX3r: ident, $cmp3x: ident, [ $( ( $cr3_trigger: ident: $cr3_trigger_bits: expr) ) ,* ] , [ $ ( ( $cr3_event_dst : ident , $cr3_tim_event_index : expr ) ) , * ] ] ,
79+ [ $cmpX4r: ident, $cmp4x: ident, [ $( ( $cr4_trigger: ident: $cr4_trigger_bits: expr) ) ,* ] , [ $ ( ( $cr4_event_dst : ident , $cr4_tim_event_index : expr ) ) , * ] ]
4980 ] ) ,+) => { $(
50- hrtim_cr_helper!( $TIMX: HrCr1 : $cmpX1r, $cmp1x, $( ( $cr1_trigger: $cr1_trigger_bits) ) ,* ) ;
51- hrtim_cr_helper!( $TIMX: HrCr2 : $cmpX2r, $cmp2x, $( ( $cr2_trigger: $cr2_trigger_bits) ) ,* ) ;
52- hrtim_cr_helper!( $TIMX: HrCr3 : $cmpX3r, $cmp3x, $( ( $cr3_trigger: $cr3_trigger_bits) ) ,* ) ;
53- hrtim_cr_helper!( $TIMX: HrCr4 : $cmpX4r, $cmp4x, $( ( $cr4_trigger: $cr4_trigger_bits) ) ,* ) ;
81+ hrtim_cr_helper!( $TIMX: HrCr1 : $cmpX1r, $cmp1x, [ $( ( $cr1_trigger: $cr1_trigger_bits) ) ,* ] , [ $ ( ( $cr1_event_dst , $cr1_tim_event_index ) ) , * ] , 3 ) ;
82+ hrtim_cr_helper!( $TIMX: HrCr2 : $cmpX2r, $cmp2x, [ $( ( $cr2_trigger: $cr2_trigger_bits) ) ,* ] , [ $ ( ( $cr2_event_dst , $cr2_tim_event_index ) ) , * ] , 4 ) ;
83+ hrtim_cr_helper!( $TIMX: HrCr3 : $cmpX3r, $cmp3x, [ $( ( $cr3_trigger: $cr3_trigger_bits) ) ,* ] , [ $ ( ( $cr3_event_dst , $cr3_tim_event_index ) ) , * ] , 5 ) ;
84+ hrtim_cr_helper!( $TIMX: HrCr4 : $cmpX4r, $cmp4x, [ $( ( $cr4_trigger: $cr4_trigger_bits) ) ,* ] , [ $ ( ( $cr4_event_dst , $cr4_tim_event_index ) ) , * ] , 6 ) ;
5485 ) +} ;
5586}
5687
88+ // See RM0440 Table 218. 'Events mapping across timer A to F'
5789hrtim_cr ! {
5890 HRTIM_MASTER : [
59- [ mcmp1r, mcmp1, ( Adc13 : 1 << 0 ) , ( Adc24 : 1 << 0 ) , ( Adc579 : 0 ) , ( Adc6810 : 0 ) ] ,
60- [ mcmp2r, mcmp2, ( Adc13 : 1 << 1 ) , ( Adc24 : 1 << 1 ) , ( Adc579 : 1 ) , ( Adc6810 : 1 ) ] ,
61- [ mcmp3r, mcmp3, ( Adc13 : 1 << 2 ) , ( Adc24 : 1 << 2 ) , ( Adc579 : 2 ) , ( Adc6810 : 2 ) ] ,
62- [ mcmp4r, mcmp4, ( Adc13 : 1 << 3 ) , ( Adc24 : 1 << 3 ) , ( Adc579 : 3 ) , ( Adc6810 : 3 ) ]
91+ [ mcmp1r, mcmp1, [ ( Adc13 : 1 << 0 ) , ( Adc24 : 1 << 0 ) , ( Adc579 : 0 ) , ( Adc6810 : 0 ) ] , [ ] ] ,
92+ [ mcmp2r, mcmp2, [ ( Adc13 : 1 << 1 ) , ( Adc24 : 1 << 1 ) , ( Adc579 : 1 ) , ( Adc6810 : 1 ) ] , [ ] ] ,
93+ [ mcmp3r, mcmp3, [ ( Adc13 : 1 << 2 ) , ( Adc24 : 1 << 2 ) , ( Adc579 : 2 ) , ( Adc6810 : 2 ) ] , [ ] ] ,
94+ [ mcmp4r, mcmp4, [ ( Adc13 : 1 << 3 ) , ( Adc24 : 1 << 3 ) , ( Adc579 : 3 ) , ( Adc6810 : 3 ) ] , [ ] ]
6395 ] ,
6496
6597 HRTIM_TIMA : [
66- [ cmp1ar, cmp1x, ] ,
67- [ cmp2ar, cmp2x, ( Adc24 : 1 << 10 ) , ( Adc6810 : 10 ) ] ,
68- [ cmp3ar, cmp3x, ( Adc13 : 1 << 11 ) , ( Adc579 : 10 ) ] ,
69- [ cmp4ar, cmp4x, ( Adc13 : 1 << 12 ) , ( Adc24 : 1 << 12 ) , ( Adc579 : 11 ) , ( Adc6810 : 11 ) ]
98+ [ cmp1ar, cmp1x, [ ] , [ ( HRTIM_TIMB , 1 ) , ( HRTIM_TIMD , 1 ) ] ] ,
99+ [ cmp2ar, cmp2x, [ ( Adc24 : 1 << 10 ) , ( Adc6810 : 10 ) ] , [ ( HRTIM_TIMB , 2 ) , ( HRTIM_TIMC , 1 ) ] ] ,
100+ [ cmp3ar, cmp3x, [ ( Adc13 : 1 << 11 ) , ( Adc579 : 10 ) ] , [ ( HRTIM_TIMC , 2 ) , ( HRTIM_TIMF , 1 ) ] ] ,
101+ [ cmp4ar, cmp4x, [ ( Adc13 : 1 << 12 ) , ( Adc24 : 1 << 12 ) , ( Adc579 : 11 ) , ( Adc6810 : 11 ) ] , [ ( HRTIM_TIMD , 2 ) , ( HRTIM_TIME , 1 ) ] ]
70102 ] ,
71103
72104 HRTIM_TIMB : [
73- [ cmp1br, cmp1x, ] ,
74- [ cmp2br, cmp2x, ( Adc24 : 1 << 14 ) , ( Adc6810 : 13 ) ] ,
75- [ cmp3br, cmp3x, ( Adc13 : 1 << 16 ) , ( Adc579 : 14 ) ] ,
76- [ cmp4br, cmp4x, ( Adc13 : 1 << 17 ) , ( Adc24 : 1 << 16 ) , ( Adc579 : 15 ) , ( Adc6810 : 14 ) ]
105+ [ cmp1br, cmp1x, [ ] , [ ( HRTIM_TIMA , 1 ) , ( HRTIM_TIMF , 2 ) ] ] ,
106+ [ cmp2br, cmp2x, [ ( Adc24 : 1 << 14 ) , ( Adc6810 : 13 ) ] , [ ( HRTIM_TIMA , 2 ) , ( HRTIM_TIMC , 3 ) , ( HRTIM_TIMD , 3 ) ] ] ,
107+ [ cmp3br, cmp3x, [ ( Adc13 : 1 << 16 ) , ( Adc579 : 14 ) ] , [ ( HRTIM_TIMC , 4 ) , ( HRTIM_TIME , 2 ) ] ] ,
108+ [ cmp4br, cmp4x, [ ( Adc13 : 1 << 17 ) , ( Adc24 : 1 << 16 ) , ( Adc579 : 15 ) , ( Adc6810 : 14 ) ] , [ ( HRTIM_TIMD , 4 ) , ( HRTIM_TIME , 3 ) , ( HRTIM_TIMF , 3 ) ] ]
77109 ] ,
78110
79111 HRTIM_TIMC : [
80- [ cmp1cr, cmp1x, ] ,
81- [ cmp2cr, cmp2x, ( Adc24 : 1 << 18 ) , ( Adc6810 : 16 ) ] ,
82- [ cmp3cr, cmp3x, ( Adc13 : 1 << 21 ) , ( Adc579 : 18 ) ] ,
83- [ cmp4cr, cmp4x, ( Adc13 : 1 << 22 ) , ( Adc24 : 1 << 20 ) , ( Adc579 : 19 ) , ( Adc6810 : 17 ) ]
112+ [ cmp1cr, cmp1x, [ ] , [ ( HRTIM_TIME , 4 ) , ( HRTIM_TIMF , 4 ) ] ] ,
113+ [ cmp2cr, cmp2x, [ ( Adc24 : 1 << 18 ) , ( Adc6810 : 16 ) ] , [ ( HRTIM_TIMA , 3 ) , ( HRTIM_TIME , 5 ) ] ] ,
114+ [ cmp3cr, cmp3x, [ ( Adc13 : 1 << 21 ) , ( Adc579 : 18 ) ] , [ ( HRTIM_TIMA , 4 ) , ( HRTIM_TIMB , 3 ) ] ] ,
115+ [ cmp4cr, cmp4x, [ ( Adc13 : 1 << 22 ) , ( Adc24 : 1 << 20 ) , ( Adc579 : 19 ) , ( Adc6810 : 17 ) ] , [ ( HRTIM_TIMB , 4 ) , ( HRTIM_TIMD , 5 ) , ( HRTIM_TIMF , 5 ) ] ]
84116 ] ,
85117
86118 HRTIM_TIMD : [
87- [ cmp1dr, cmp1x, ] ,
88- [ cmp2dr, cmp2x, ( Adc24 : 1 << 23 ) , ( Adc6810 : 20 ) ] ,
89- [ cmp3dr, cmp3x, ( Adc13 : 1 << 25 ) , ( Adc579 : 21 ) ] ,
90- [ cmp4dr, cmp4x, ( Adc13 : 1 << 26 ) , ( Adc24 : 1 << 25 ) , ( Adc579 : 22 ) , ( Adc6810 : 21 ) ]
119+ [ cmp1dr, cmp1x, [ ] , [ ( HRTIM_TIMA , 5 ) , ( HRTIM_TIME , 6 ) ] ] ,
120+ [ cmp2dr, cmp2x, [ ( Adc24 : 1 << 23 ) , ( Adc6810 : 20 ) ] , [ ( HRTIM_TIMA , 6 ) , ( HRTIM_TIMC , 5 ) , ( HRTIM_TIME , 7 ) ] ] ,
121+ [ cmp3dr, cmp3x, [ ( Adc13 : 1 << 25 ) , ( Adc579 : 21 ) ] , [ ( HRTIM_TIMB , 5 ) , ( HRTIM_TIMF , 6 ) ] ] ,
122+ [ cmp4dr, cmp4x, [ ( Adc13 : 1 << 26 ) , ( Adc24 : 1 << 25 ) , ( Adc579 : 22 ) , ( Adc6810 : 21 ) ] , [ ( HRTIM_TIMB , 6 ) , ( HRTIM_TIMC , 6 ) , ( HRTIM_TIMF , 7 ) ] ]
91123 ] ,
92124
93125 HRTIM_TIME : [
94- [ cmp1er, cmp1x, ] ,
95- [ cmp2er, cmp2x, ( Adc24 : 1 << 28 ) , ( Adc6810 : 24 ) ] ,
96- [ cmp3er, cmp3x, ( Adc13 : 1 << 29 ) , ( Adc24 : 1 << 29 ) , ( Adc579 : 24 ) , ( Adc6810 : 25 ) ] ,
97- [ cmp4er, cmp4x, ( Adc13 : 1 << 30 ) , ( Adc24 : 1 << 30 ) , ( Adc579 : 25 ) , ( Adc6810 : 26 ) ]
126+ [ cmp1er, cmp1x, [ ] , [ ( HRTIM_TIMB , 7 ) , ( HRTIM_TIMD , 6 ) ] ] ,
127+ [ cmp2er, cmp2x, [ ( Adc24 : 1 << 28 ) , ( Adc6810 : 24 ) ] , [ ( HRTIM_TIMB , 8 ) , ( HRTIM_TIMF , 8 ) ] ] ,
128+ [ cmp3er, cmp3x, [ ( Adc13 : 1 << 29 ) , ( Adc24 : 1 << 29 ) , ( Adc579 : 24 ) , ( Adc6810 : 25 ) ] , [ ( HRTIM_TIMA , 7 ) , ( HRTIM_TIMC , 7 ) , ( HRTIM_TIMF , 9 ) ] ] ,
129+ [ cmp4er, cmp4x, [ ( Adc13 : 1 << 30 ) , ( Adc24 : 1 << 30 ) , ( Adc579 : 25 ) , ( Adc6810 : 26 ) ] , [ ( HRTIM_TIMA , 8 ) , ( HRTIM_TIMC , 8 ) , ( HRTIM_TIMD , 7 ) ] ]
98130 ] ,
99131
100132 HRTIM_TIMF : [
101- [ cmp1fr, cmp1x, ( Adc24 : 1 << 15 ) ] ,
102- [ cmp2fr, cmp2x, ( Adc13 : 1 << 10 ) , ( Adc24 : 1 << 11 ) , ( Adc579 : 27 ) , ( Adc6810 : 28 ) ] ,
103- [ cmp3fr, cmp3x, ( Adc13 : 1 << 15 ) , ( Adc579 : 28 ) , ( Adc6810 : 29 ) ] ,
104- [ cmp4fr, cmp4x, ( Adc13 : 1 << 20 ) , ( Adc24 : 1 << 19 ) , ( Adc579 : 29 ) , ( Adc6810 : 30 ) ]
133+ [ cmp1fr, cmp1x, [ ( Adc24 : 1 << 15 ) ] , [ ( HRTIM_TIMD , 8 ) ] ] ,
134+ [ cmp2fr, cmp2x, [ ( Adc13 : 1 << 10 ) , ( Adc24 : 1 << 11 ) , ( Adc579 : 27 ) , ( Adc6810 : 28 ) ] , [ ( HRTIM_TIMC , 9 ) ] ] ,
135+ [ cmp3fr, cmp3x, [ ( Adc13 : 1 << 15 ) , ( Adc579 : 28 ) , ( Adc6810 : 29 ) ] , [ ( HRTIM_TIMB , 9 ) , ( HRTIM_TIMD , 9 ) , ( HRTIM_TIME , 8 ) ] ] ,
136+ [ cmp4fr, cmp4x, [ ( Adc13 : 1 << 20 ) , ( Adc24 : 1 << 19 ) , ( Adc579 : 29 ) , ( Adc6810 : 30 ) ] , [ ( HRTIM_TIMA , 9 ) , ( HRTIM_TIME , 9 ) ] ]
105137 ]
106138}
139+
140+ macro_rules! hrtim_master_cr {
141+ ( $( $cr_type: ident: $cr_index: expr) ,* ) => { $(
142+ /// Compare match event for neighbor timer
143+ impl <DST , PSCL > super :: event:: EventSource <DST , PSCL > for $cr_type<HRTIM_MASTER , PSCL > {
144+ const BITS : u32 = 1 << ( $cr_index + 7 ) ; // MSTCMP1 is at bit 8 etc
145+ }
146+
147+ impl <DST , PSCL > super :: event:: TimerResetEventSource <DST , PSCL > for $cr_type<HRTIM_MASTER , PSCL > {
148+ const BITS : u32 = 1 << ( $cr_index + 4 ) ; // MSTCMP1 is at bit 5
149+ }
150+ ) * } ;
151+ }
152+
153+ hrtim_master_cr ! {
154+ HrCr1 : 1 ,
155+ HrCr2 : 2 ,
156+ HrCr3 : 3 ,
157+ HrCr4 : 4
158+ }
159+
160+ macro_rules! hrtim_timer_rst {
161+ ( $( $TIMX: ident: $cr_type: ident: $bit_index: literal) ,* ) => { $(
162+ impl <DST , PSCL > super :: event:: TimerResetEventSource <DST , PSCL > for $cr_type<$TIMX, PSCL > {
163+ const BITS : u32 = 1 << $bit_index;
164+ }
165+ ) * } ;
166+ }
167+
168+ hrtim_timer_rst ! {
169+ HRTIM_TIMA : HrCr2 : 2 ,
170+ HRTIM_TIMA : HrCr4 : 3 ,
171+
172+ HRTIM_TIMB : HrCr2 : 2 ,
173+ HRTIM_TIMB : HrCr4 : 3 ,
174+
175+ HRTIM_TIMC : HrCr2 : 2 ,
176+ HRTIM_TIMC : HrCr4 : 3 ,
177+
178+ HRTIM_TIMD : HrCr2 : 2 ,
179+ HRTIM_TIMD : HrCr4 : 3 ,
180+
181+ HRTIM_TIME : HrCr2 : 2 ,
182+ HRTIM_TIME : HrCr4 : 3 ,
183+
184+ HRTIM_TIMF : HrCr2 : 2 ,
185+ HRTIM_TIMF : HrCr4 : 3
186+ }
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