fmt

Author: usbalbin

src/dma/stream.rs

@@ -508,28 +508,15 @@ macro_rules! dma_stream {
     };
 }
 
-
 dma_stream!(
     // Note: the field names start from one, unlike the RM where they start from
     // zero. May need updating if it gets fixed upstream.
-    (
-        Stream0, 0, 1
-    ),
-    (
-        Stream1, 1, 2
-    ),
-    (
-        Stream2, 2, 3
-    ),
-    (
-        Stream3, 3, 4
-    ),
-    (
-        Stream4, 4, 5
-    ),
-    (
-        Stream5, 5, 6
-    ),
+    (Stream0, 0, 1),
+    (Stream1, 1, 2),
+    (Stream2, 2, 3),
+    (Stream3, 3, 4),
+    (Stream4, 4, 5),
+    (Stream5, 5, 6),
 );
 
 // Cat 3 and 4 devices
@@ -545,10 +532,6 @@ dma_stream!(
 dma_stream!(
     // Note: the field names start from one, unlike the RM where they start from
     // zero. May need updating if it gets fixed upstream.
-    (
-        Stream6, 6, 7
-    ),
-    (
-        Stream7, 7, 8
-    ),
+    (Stream6, 6, 7),
+    (Stream7, 7, 8),
 );

src/independent_watchdog.rs

@@ -93,7 +93,7 @@ impl IndependentWatchdog {
         }
         self.iwdg
             .winr()
-            .write(|w| unsafe { w.win().bits(Self::MAX_COUNTER_VALUE as u16) } );
+            .write(|w| unsafe { w.win().bits(Self::MAX_COUNTER_VALUE as u16) });
 
         // Calculate the counter values
         let reload_value = max_window_time.to_millis() * (Self::CLOCK_SPEED / 1000)
@@ -105,7 +105,9 @@ impl IndependentWatchdog {
         while self.iwdg.sr().read().rvu().bit_is_set() {
             cortex_m::asm::nop();
         }
-        self.iwdg.rlr().write(|w| unsafe { w.rl().bits(reload_value as u16) });
+        self.iwdg
+            .rlr()
+            .write(|w| unsafe { w.rl().bits(reload_value as u16) });
 
         self.feed();
         // Enable register access