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Update DMA for new pac
1 parent fccd81e commit 6af2cef

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+48
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‎src/dma/stream.rs

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ impl<I: Instance> StreamsTuple<I> {
176176
// the stream
177177
macro_rules! dma_stream {
178178
($(($name:ident, $number:expr,
179-
regs => $ccr:ident, $cparX:ident, $cmarX:ident, $cndtrX:ident,
179+
regs => $chX:ident,
180180
fields => $tcif:ident, $htif:ident, $teif:ident, $gif:ident, $tcisr:ident, $htisr:ident, $teisr:ident, $gisr:ident,
181181
dmamux => $cXcr:ident,)
182182
),+$(,)*) => {
@@ -253,28 +253,28 @@ macro_rules! dma_stream {
253253
#[inline(always)]
254254
unsafe fn enable(&mut self) {
255255
//NOTE(unsafe) We only access the registers that belongs to the StreamX
256-
let dma = &*I::ptr();
257-
dma.$ccr.modify(|_, w| w.en().set_bit());
256+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
257+
dma_ch.cr.modify(|_, w| w.en().set_bit());
258258
}
259259

260260
#[inline(always)]
261261
fn is_enabled() -> bool {
262262
//NOTE(unsafe) Atomic read with no side effects
263-
let dma = unsafe { &*I::ptr() };
264-
dma.$ccr.read().en().bit_is_set()
263+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
264+
dma_ch.cr.read().en().bit_is_set()
265265
}
266266

267267
fn disable(&mut self) {
268268
if Self::is_enabled() {
269269
//NOTE(unsafe) We only access the registers that belongs to the StreamX
270-
let dma = unsafe { &*I::ptr() };
270+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
271271

272272
// Aborting an on-going transfer might cause interrupts to fire, disable
273273
// them
274274
let interrupts = Self::get_interrupts_enable();
275275
self.disable_interrupts();
276276

277-
dma.$ccr.modify(|_, w| w.en().clear_bit());
277+
dma_ch.cr.modify(|_, w| w.en().clear_bit());
278278
while Self::is_enabled() {}
279279

280280
self.clear_interrupts();
@@ -295,14 +295,14 @@ macro_rules! dma_stream {
295295
#[inline(always)]
296296
fn set_priority(&mut self, priority: config::Priority) {
297297
//NOTE(unsafe) We only access the registers that belongs to the StreamX
298-
let dma = unsafe { &*I::ptr() };
299-
dma.$ccr.modify(|_, w| unsafe { w.pl().bits(priority.bits()) });
298+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
299+
dma_ch.cr.modify(|_, w| unsafe { w.pl().bits(priority.bits()) });
300300
}
301301

302302
#[inline(always)]
303303
fn disable_interrupts(&mut self) {
304304
//NOTE(unsafe) We only access the registers that belongs to the StreamX
305-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
305+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
306306
dmacr.modify(|_, w| w
307307
.tcie().clear_bit()
308308
.teie().clear_bit()
@@ -314,8 +314,8 @@ macro_rules! dma_stream {
314314
#[inline(always)]
315315
fn enable_interrupts(&mut self, interrupt: Self::Interrupts) {
316316
//NOTE(unsafe) We only access the registers that belongs to the StreamX
317-
let dma = unsafe { &*I::ptr() };
318-
dma.$ccr.modify(|_, w| w
317+
let dma_ch = &unsafe { &*I::ptr() }.$chX();
318+
dma_ch.cr.modify(|_, w| w
319319
.tcie().bit(interrupt.transfer_complete)
320320
.teie().bit(interrupt.transfer_error)
321321
.htie().bit(interrupt.half_transfer)
@@ -325,8 +325,8 @@ macro_rules! dma_stream {
325325
#[inline(always)]
326326
fn get_interrupts_enable() -> Self::Interrupts {
327327
//NOTE(unsafe) We only access the registers that belongs to the StreamX
328-
let dma = unsafe { &*I::ptr() };
329-
let cr = dma.$ccr.read();
328+
let dma_ch = unsafe { &*I::ptr() }.$chX();
329+
let cr = dma_ch.cr.read();
330330

331331
DmaInterrupts {
332332
transfer_complete: cr.tcie().bit_is_set(),
@@ -339,7 +339,7 @@ macro_rules! dma_stream {
339339
#[inline(always)]
340340
fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool) {
341341
//NOTE(unsafe) We only access the registers that belongs to the StreamX
342-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
342+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
343343
dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt));
344344
let _ = dmacr.read();
345345
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -348,7 +348,7 @@ macro_rules! dma_stream {
348348
#[inline(always)]
349349
fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool) {
350350
//NOTE(unsafe) We only access the registers that belongs to the StreamX
351-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
351+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
352352
dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt));
353353
let _ = dmacr.read();
354354
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -357,7 +357,7 @@ macro_rules! dma_stream {
357357
#[inline(always)]
358358
fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) {
359359
//NOTE(unsafe) We only access the registers that belongs to the StreamX
360-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
360+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
361361
dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt));
362362
let _ = dmacr.read();
363363
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -383,70 +383,70 @@ macro_rules! dma_stream {
383383
#[inline(always)]
384384
unsafe fn set_peripheral_address(&mut self, value: u32) {
385385
//NOTE(unsafe) We only access the registers that belongs to the StreamX
386-
let dma = &*I::ptr();
387-
dma.$cparX.write(|w| w.pa().bits(value));
386+
let dma_ch = unsafe { &*I::ptr() }.$chX();
387+
dma_ch.par.write(|w| w.pa().bits(value));
388388
}
389389

390390
#[inline(always)]
391391
unsafe fn set_memory_address(&mut self, value: u32) {
392392
//NOTE(unsafe) We only access the registers that belongs to the StreamX
393-
let dma = &*I::ptr();
394-
dma.$cmarX.write(|w| w.ma().bits(value) );
393+
let dma_ch = unsafe { &*I::ptr() }.$chX();
394+
dma_ch.mar.write(|w| w.ma().bits(value) );
395395
}
396396

397397
#[inline(always)]
398398
fn get_memory_address(&self) -> u32 {
399399
//NOTE(unsafe) We only access the registers that belongs to the StreamX
400-
let dma = unsafe { &*I::ptr() };
401-
dma.$cmarX.read().ma().bits()
400+
let dma_ch = unsafe { &*I::ptr() }.$chX();
401+
dma_ch.mar.read().ma().bits()
402402
}
403403

404404
#[inline(always)]
405405
fn set_number_of_transfers(&mut self, value: u16) {
406406
//NOTE(unsafe) We only access the registers that belongs to the StreamX
407-
let dma = unsafe { &*I::ptr() };
408-
dma.$cndtrX.write(|w| unsafe {w.ndt().bits(value) });
407+
let dma_ch = unsafe { &*I::ptr() }.$chX();
408+
dma_ch.ndtr.write(|w| unsafe {w.ndt().bits(value) });
409409
}
410410

411411
#[inline(always)]
412412
fn get_number_of_transfers() -> u16 {
413413
//NOTE(unsafe) We only access the registers that belongs to the StreamX
414-
let dma = unsafe { &*I::ptr() };
415-
dma.$cndtrX.read().ndt().bits()
414+
let dma_ch = unsafe { &*I::ptr() }.$chX();
415+
dma_ch.ndtr.read().ndt().bits()
416416
}
417417
#[inline(always)]
418418
unsafe fn set_memory_size(&mut self, size: u8) {
419419
//NOTE(unsafe) We only access the registers that belongs to the StreamX
420-
let dma = &*I::ptr();
421-
dma.$ccr.modify(|_, w| w.msize().bits(size));
420+
let dma_ch = unsafe { &*I::ptr() }.$chX();
421+
dma_ch.cr.modify(|_, w| w.msize().bits(size));
422422
}
423423

424424
#[inline(always)]
425425
unsafe fn set_peripheral_size(&mut self, size: u8) {
426426
//NOTE(unsafe) We only access the registers that belongs to the StreamX
427-
let dma = &*I::ptr();
428-
dma.$ccr.modify(|_, w| w.psize().bits(size));
427+
let dma_ch = unsafe { &*I::ptr() }.$chX();
428+
dma_ch.cr.modify(|_, w| w.psize().bits(size));
429429
}
430430

431431
#[inline(always)]
432432
fn set_memory_increment(&mut self, increment: bool) {
433433
//NOTE(unsafe) We only access the registers that belongs to the StreamX
434-
let dma = unsafe { &*I::ptr() };
435-
dma.$ccr.modify(|_, w| w.minc().bit(increment));
434+
let dma_ch = unsafe { &*I::ptr() }.$chX();
435+
dma_ch.cr.modify(|_, w| w.minc().bit(increment));
436436
}
437437

438438
#[inline(always)]
439439
fn set_peripheral_increment(&mut self, increment: bool) {
440440
//NOTE(unsafe) We only access the registers that belongs to the StreamX
441-
let dma = unsafe { &*I::ptr() };
442-
dma.$ccr.modify(|_, w| w.pinc().bit(increment));
441+
let dma_ch = unsafe { &*I::ptr() }.$chX();
442+
dma_ch.cr.modify(|_, w| w.pinc().bit(increment));
443443
}
444444

445445
#[inline(always)]
446446
fn set_direction(&mut self, direction: DmaDirection) {
447447
//NOTE(unsafe) We only access the registers that belongs to the StreamX
448-
let dma = unsafe { &*I::ptr() };
449-
dma.$ccr.modify(|_, w| {
448+
let dma_ch = unsafe { &*I::ptr() }.$chX();
449+
dma_ch.cr.modify(|_, w| {
450450
match direction {
451451
DmaDirection::PeripheralToMemory =>
452452
w.dir().clear_bit().mem2mem().clear_bit(),
@@ -461,8 +461,8 @@ macro_rules! dma_stream {
461461
#[inline(always)]
462462
fn set_circular_buffer(&mut self, circular_buffer: bool) {
463463
//NOTE(unsafe) We only access the registers that belongs to the StreamX
464-
let dma = unsafe { &*I::ptr() };
465-
dma.$ccr.modify(|_, w| w.circ().bit(circular_buffer));
464+
let dma_ch = unsafe { &*I::ptr() }.$chX();
465+
dma_ch.cr.modify(|_, w| w.circ().bit(circular_buffer));
466466
}
467467
}
468468

@@ -487,7 +487,7 @@ macro_rules! dma_stream {
487487
#[inline(always)]
488488
pub fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) {
489489
//NOTE(unsafe) We only access the registers that belongs to the StreamX
490-
let dmacr = &unsafe { &*I::ptr() }.$ccr;
490+
let dmacr = &unsafe { &*I::ptr() }.$chX().cr;
491491
dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt));
492492
let _ = dmacr.read();
493493
let _ = dmacr.read(); // Delay 2 peripheral clocks
@@ -502,49 +502,49 @@ dma_stream!(
502502
// zero. May need updating if it gets fixed upstream.
503503
(
504504
Stream0, 0,
505-
regs => ccr1, cpar1, cmar1, cndtr1,
505+
regs => ch1,
506506
fields => tcif1, htif1, teif1, gif1, tcif1, htif1, teif1, gif1,
507507
dmamux => c0cr,
508508
),
509509
(
510510
Stream1, 1,
511-
regs => ccr2, cpar2, cmar2, cndtr2,
511+
regs => ch2,
512512
fields => tcif2, htif2, teif2, gif2, tcif2, htif2, teif2, gif2,
513513
dmamux => c1cr,
514514
),
515515
(
516516
Stream2, 2,
517-
regs => ccr3, cpar3, cmar3, cndtr3,
517+
regs => ch3,
518518
fields => tcif3, htif3, teif3, gif3, tcif3, htif3, teif3, gif3,
519519
dmamux => c2cr,
520520
),
521521
(
522522
Stream3, 3,
523-
regs => ccr4, cpar4, cmar4, cndtr4,
523+
regs => ch4,
524524
fields => tcif4, htif4, teif4, gif4, tcif4, htif4, teif4, gif4,
525525
dmamux => c3cr,
526526
),
527527
(
528528
Stream4, 4,
529-
regs => ccr5, cpar5, cmar5, cndtr5,
529+
regs => ch5,
530530
fields => tcif5, htif5, teif5, gif5, tcif5, htif5, teif5, gif5,
531531
dmamux => c4cr,
532532
),
533533
(
534534
Stream5, 5,
535-
regs => ccr6, cpar6, cmar6, cndtr6,
535+
regs => ch6,
536536
fields => tcif6, htif6, teif6, gif6, tcif6, htif6, teif6, gif6,
537537
dmamux => c5cr,
538538
),
539539
(
540540
Stream6, 6,
541-
regs => ccr7, cpar7, cmar7, cndtr7,
541+
regs => ch7,
542542
fields => tcif7, htif7, teif7, gif7, tcif7, htif7, teif7, gif7,
543543
dmamux => c6cr,
544544
),
545545
(
546546
Stream7, 7,
547-
regs => ccr8, cpar8, cmar8, cndtr8,
547+
regs => ch8,
548548
fields => tcif8, htif8, teif8, gif8, tcif8, htif8, teif8, gif8,
549549
dmamux => c7cr,
550550
),

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