fix (spi): fix spi, add hal-1 example

Fixed visibility of methods set_bidi and set_tx_only, which were not
supposed to be public
Fixed SPI reads never happening at all because of a broken pointer cast

Author: techmccat

examples/spi-hal-one.rs

@@ -0,0 +1,107 @@
+// This example is to test the SPI without any external devices,
+// it writes to the MOSI line and logs whatever is received on the MISO line
+//
+// MISO and MOSI should be connected to make the assertions work
+
+#![no_main]
+#![no_std]
+
+use crate::hal::{
+    prelude::*,
+    pwr::PwrExt,
+    rcc::Config,
+    spi,
+    stm32::Peripherals,
+    time::RateExtU32,
+};
+
+use cortex_m_rt::entry;
+use stm32g4xx_hal as hal;
+
+#[macro_use]
+mod utils;
+use utils::logger::info;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+    info!("Logger init");
+
+    let dp = Peripherals::take().unwrap();
+    let rcc = dp.RCC.constrain();
+    let pwr = dp.PWR.constrain().freeze();
+    let mut rcc = rcc.freeze(
+        Config::hsi(),
+        pwr
+    );
+
+    // let gpioa = dp.GPIOA.split(&mut rcc);
+    let gpioa = dp.GPIOA.split(&mut rcc);
+    let sclk = gpioa.pa5.into_alternate();
+    let miso = gpioa.pa6.into_alternate();
+    let mosi = gpioa.pa7.into_alternate();
+
+    // 1/8 SPI/SysClk ratio seems to be the upper limit for continuous transmission
+    // one byte at a time
+    // 1/4 works well when writing two packed bytes at once
+    // At 1/2 the clock stays on for ~80% of the time
+    let mut spi = dp
+        .SPI1
+        .spi((sclk, miso, mosi), spi::MODE_0, 8.MHz(), &mut rcc);
+    let mut cs = gpioa.pa8.into_push_pull_output();
+    cs.set_high();
+
+    // Odd number of bits to test packing edge case
+    const MESSAGE: &[u8] = "Hello world, but longer".as_bytes();
+    cs.set_low();
+    spi.write(MESSAGE).unwrap();
+    SpiBus::<u8>::flush(&mut spi).unwrap();
+    cs.set_high();
+
+    let received = &mut [0u8; MESSAGE.len()];
+    spi.read(received).unwrap();
+
+    cortex_m::asm::delay(100);
+    cs.set_low();
+    spi.transfer(received, MESSAGE).unwrap();
+    // downside of having 8 and 16 bit impls on the same struct is you have to specify which flush
+    // impl to call, although internally they call the same function
+    SpiBus::<u8>::flush(&mut spi).unwrap();
+    cs.set_high();
+    
+    info!("Received {:?}", core::str::from_utf8(received).ok());
+    assert_eq!(MESSAGE, received);
+
+    cs.set_low();
+    spi.transfer_in_place(received).unwrap();
+    SpiBus::<u8>::flush(&mut spi).unwrap();
+    cs.set_high();
+
+    info!("Received {:?}", core::str::from_utf8(received).ok());
+    assert_eq!(MESSAGE, received);
+
+    // Switch between 8 and 16 bit frames on the fly
+    const TX_16B: &[u16] = &[0xf00f, 0xfeef, 0xfaaf];
+    let rx_16b = &mut [0u16; TX_16B.len()];
+
+    cs.set_low();
+    spi.transfer(rx_16b, TX_16B).unwrap();
+    // internally works the same as SpiBus::<u8>::flush()
+    SpiBus::<u16>::flush(&mut spi).unwrap();
+    cs.set_high();
+
+    info!("Received {:?}", rx_16b);
+    assert_eq!(TX_16B, rx_16b);
+
+    cs.set_low();
+    spi.transfer_in_place(rx_16b).unwrap();
+    SpiBus::<u16>::flush(&mut spi).unwrap();
+    cs.set_high();
+
+    info!("Received {:?}", rx_16b);
+    assert_eq!(TX_16B, rx_16b);
+
+    loop {
+        cortex_m::asm::nop();
+    }
+}

src/spi.rs

@@ -186,20 +186,24 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
     fn read_unchecked<W: FrameSize>(&mut self) -> W {
         // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
         // reading a half-word)
-        unsafe { ptr::read_volatile(&self.spi.dr() as *const _ as *const W) }
+        unsafe { ptr::read_volatile(self.spi.dr().as_ptr() as *const W) }
     }
     #[inline]
     fn write_unchecked<W: FrameSize>(&mut self, word: W) {
         // NOTE(write_volatile) see note above
         let dr = self.spi.dr().as_ptr() as *mut W;
         unsafe { ptr::write_volatile(dr, word) };
     }
+    /// disables rx
     #[inline]
     pub fn set_tx_only(&mut self) {
+        // very counter-intuitively, setting spi bidi mode on disables rx while transmitting
+        // it's made for half-duplex spi, which they called bidirectional in the manual
         self.spi
             .cr1()
             .modify(|_, w| w.bidimode().bidirectional().bidioe().output_enabled());
     }
+    /// re-enables rx if it was disabled
     #[inline]
     pub fn set_bidi(&mut self) {
         self.spi
@@ -314,6 +318,7 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
         self.set_bidi();
 
         let half_len = len / 2;
+        // leftover write/read operation because bytes are not a multiple of 2
         let pair_left = len % 2;
 
         // prefill write fifo so that the clock doen't stop while fetch the read byte