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Fix comp_w_dac example
1 parent 312436d commit 845448e

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3 files changed

+12
-7
lines changed

3 files changed

+12
-7
lines changed

examples/comp_w_dac.rs

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ mod utils;
77
extern crate cortex_m_rt as rt;
88

99
use rt::entry;
10+
use stm32g4xx_hal::observable::Observable;
1011

1112
#[entry]
1213
fn main() -> ! {
@@ -30,15 +31,16 @@ fn main() -> ! {
3031
// Set up DAC to output to pa4 and to internal signal Dac1IntSig1
3132
// which just so happens is compatible with comp1
3233
let dac1ch1 = dp.DAC1.constrain((gpioa.pa4, Dac1IntSig1), &mut rcc);
33-
let mut dac = dac1ch1.calibrate_buffer(&mut delay).enable();
34+
let dac = dac1ch1.calibrate_buffer(&mut delay).enable();
35+
let (mut dac, [dac_token]) = dac.observe();
3436

3537
let (comp1, _comp2, ..) = dp.COMP.split(&mut rcc);
3638
let pa1 = gpioa.pa1.into_analog();
3739

3840
// Set up comparator with pa1 as positive, and the DAC as negative input
3941
let comp = comp1.comparator(
40-
&pa1,
41-
&dac,
42+
pa1,
43+
dac_token,
4244
comparator::Config::default().hysteresis(comparator::Hysteresis::None),
4345
&rcc.clocks,
4446
);
@@ -59,7 +61,7 @@ fn main() -> ! {
5961
// * 0V at p1 => 0% duty
6062
// * VDDA at p1 => 100% duty
6163
loop {
62-
dac.set_value(val);
64+
dac.as_mut().set_value(val);
6365
match val {
6466
0 => dir = Direction::Upcounting,
6567
4095 => dir = Direction::Downcounting,

src/comparator.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -148,12 +148,12 @@ pub trait PositiveInput<C> {
148148
pub trait NegativeInput<C> {
149149
/// Does this input use the internal reference Vrefint
150150
///
151-
/// This only true for RefintInput
151+
/// This only true for [`RefintInput`]
152152
const USE_VREFINT: bool;
153153

154154
/// Does this input rely on dividing Vrefint using an internal resistor divider
155155
///
156-
/// This is only relevant for `RefintInput` other than `RefintInput::VRefint`
156+
/// This is only relevant for [`RefintInput`] other than [`refint_input::VRefint`]
157157
const USE_RESISTOR_DIVIDER: bool = false;
158158

159159
fn setup(comp: &mut C);
@@ -307,7 +307,7 @@ refint_input!(COMP5, COMP6, COMP7,);
307307

308308
macro_rules! dac_input_helper {
309309
($COMP:ident: $channel:ident, $MODE:ident, $bits:expr) => {
310-
impl<ED> NegativeInput<$COMP> for &dac::$channel<{ dac::$MODE }, ED> {
310+
impl<ED> NegativeInput<$COMP> for dac::$channel<{ dac::$MODE }, ED> {
311311
const USE_VREFINT: bool = false;
312312

313313
fn setup(comp: &mut $COMP) {

src/dac.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -218,6 +218,9 @@ macro_rules! dac_helper {
218218
}
219219
}
220220

221+
impl<const MODE_BITS: u8, ED> crate::Sealed for $CX<MODE_BITS, ED> { }
222+
impl<const MODE_BITS: u8, ED> crate::observable::Observable for $CX<MODE_BITS, ED> { }
223+
221224
impl<const MODE_BITS: u8, ED> $CX<MODE_BITS, ED> {
222225
/// Calibrate the DAC output buffer by performing a "User
223226
/// trimming" operation. It is useful when the VDDA/VREF+

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