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usbalbinusbalbin
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Update for new pac
1 parent a994773 commit a42558f

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8 files changed

+71
-71
lines changed

8 files changed

+71
-71
lines changed

‎src/hrtim/capture.rs‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ pub trait HrCapture {
102102
///
103103
/// where captures during down counting count as negative (before the upcount)
104104
///
105-
/// ````
105+
/// ```
106106
/// Counter
107107
/// ---------------------------------- <--- period
108108
/// \ ^ /
@@ -113,7 +113,7 @@ pub trait HrCapture {
113113
/// \|/
114114
/// <-------------- 0 --------------> t
115115
/// Negative result | positive result
116-
/// ````
116+
/// ```
117117
fn get_last_signed(&self, period: u16) -> i32 {
118118
let (value, dir) = self.get_last();
119119

@@ -159,7 +159,7 @@ macro_rules! impl_capture {
159159

160160
// SAFETY: We are the only one with access to cptXYcr
161161
unsafe {
162-
tim.$cptXYcr.modify(|r, w| w.bits(r.bits() | E::BITS));
162+
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() | E::BITS));
163163
}
164164
}
165165

@@ -169,7 +169,7 @@ macro_rules! impl_capture {
169169

170170
// SAFETY: We are the only one with access to cptXYcr
171171
unsafe {
172-
tim.$cptXYcr.modify(|r, w| w.bits(r.bits() & !E::BITS));
172+
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
173173
}
174174
}
175175

@@ -178,7 +178,7 @@ macro_rules! impl_capture {
178178
// SAFETY: We are the only one with access to cptXYcr
179179
let tim = unsafe { &*$TIMX::ptr() };
180180

181-
tim.$cptXYcr.modify(|_, w| w.swcpt().set_bit());
181+
tim.$cptXYcr().modify(|_, w| w.swcpt().set_bit());
182182
}
183183

184184
// TODO: It would be sufficient to instead of hr_control only require exclusive access to the owning timer
@@ -187,13 +187,13 @@ macro_rules! impl_capture {
187187
pub fn enable_interrupt(&mut self, enable: bool, _hr_control: &mut super::HrPwmControl) {
188188
let tim = unsafe { &*$TIMX::ptr() };
189189

190-
tim.$dier.modify(|_r, w| w.$cptXie().bit(enable));
190+
tim.$dier().modify(|_r, w| w.$cptXie().bit(enable));
191191
}
192192

193193
pub fn enable_dma(self, _ch: timer::DmaChannel<$TIMX>) -> HrCapt<$TIMX, PSCL, $CH, Dma> {
194194
// SAFETY: We own the only insance of this timers dma channel, no one else can do this
195195
let tim = unsafe { &*$TIMX::ptr() };
196-
tim.$dier.modify(|_r, w| w.$cptXde().set_bit());
196+
tim.$dier().modify(|_r, w| w.$cptXde().set_bit());
197197
HrCapt {
198198
_x: PhantomData
199199
}
@@ -203,7 +203,7 @@ macro_rules! impl_capture {
203203
impl<PSCL, DMA> HrCapture for HrCapt<$TIMX, PSCL, $CH, DMA> {
204204
fn get_last(&self) -> (u16, CountingDirection) {
205205
let tim = unsafe { &*$TIMX::ptr() };
206-
let data = tim.$cptXYr.read();
206+
let data = tim.$cptXYr().read();
207207

208208
let dir = match data.dir().bit() {
209209
true => CountingDirection::Down,
@@ -218,22 +218,22 @@ macro_rules! impl_capture {
218218
let tim = unsafe { &*$TIMX::ptr() };
219219

220220
// No need for exclusive access since this is a write only register
221-
tim.$icr.write(|w| w.$cptXc().set_bit());
221+
tim.$icr().write(|w| w.$cptXc().set_bit());
222222
}
223223

224224
fn is_pending(&self) -> bool {
225225
let tim = unsafe { &*$TIMX::ptr() };
226226

227227
// No need for exclusive access since this is a read only register
228-
tim.$isr.read().$cptX().bit()
228+
tim.$isr().read().$cptX().bit()
229229
}
230230
}
231231

232232
unsafe impl<PSCL> TargetAddress<PeripheralToMemory> for HrCapt<$TIMX, PSCL, $CH, Dma> {
233233
#[inline(always)]
234234
fn address(&self) -> u32 {
235235
let tim = unsafe { &*$TIMX::ptr() };
236-
&tim.$cptXYr as *const _ as u32
236+
&tim.$cptXYr() as *const _ as u32
237237
}
238238

239239
type MemSize = u32;

‎src/hrtim/compare_register.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,12 @@ macro_rules! hrtim_cr_helper {
4040
fn get_duty(&self) -> u16 {
4141
let tim = unsafe { &*$TIMX::ptr() };
4242

43-
tim.$cmpXYr.read().$cmpYx().bits()
43+
tim.$cmpXYr().read().$cmpYx().bits()
4444
}
4545
fn set_duty(&mut self, duty: u16) {
4646
let tim = unsafe { &*$TIMX::ptr() };
4747

48-
tim.$cmpXYr.write(|w| unsafe { w.$cmpYx().bits(duty) });
48+
tim.$cmpXYr().write(|w| unsafe { w.$cmpYx().bits(duty) });
4949
}
5050
}
5151

‎src/hrtim/control.rs‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ impl HrControltExt for HRTIM_COMMON {
2727

2828
// Start calibration procedure
2929
common
30-
.dllcr
30+
.dllcr()
3131
.write(|w| w.cal().set_bit().calen().clear_bit());
3232

3333
HrTimOngoingCalibration {
@@ -93,12 +93,12 @@ impl HrTimOngoingCalibration {
9393
// with f_hrtim at 170MHz, these settings leads to
9494
// a period of about 6.2ms
9595
common
96-
.dllcr
96+
.dllcr()
9797
.modify(|_r, w| w.calrte().bits(0b00).cal().set_bit().calen().clear_bit());
98-
common.fltinr2.write(|w| w.fltsd().bits(flt_divider as u8));
99-
common.eecr3.write(|w| w.eevsd().bits(eev_divider as u8));
98+
common.fltinr2().write(|w| w.fltsd().bits(flt_divider as u8));
99+
common.eecr3().write(|w| w.eevsd().bits(eev_divider as u8));
100100

101-
common.adcps1.write(|w| {
101+
common.adcps1().write(|w| {
102102
w.adc1psc()
103103
.bits(adc_trigger1_postscaler as u8)
104104
.adc2psc()
@@ -111,7 +111,7 @@ impl HrTimOngoingCalibration {
111111
.bits(adc_trigger5_postscaler as u8)
112112
});
113113

114-
common.adcps2.write(|w| {
114+
common.adcps2().write(|w| {
115115
w.adc6psc()
116116
.bits(adc_trigger6_postscaler as u8)
117117
.adc7psc()
@@ -130,7 +130,7 @@ impl HrTimOngoingCalibration {
130130

131131
pub fn wait_for_calibration(self) -> (HrTimCalibrated, FaultInputs, EevInputs) {
132132
let common = unsafe { &*HRTIM_COMMON::ptr() };
133-
while common.isr.read().dllrdy().bit_is_clear() {
133+
while common.isr().read().dllrdy().bit_is_clear() {
134134
// Wait until ready
135135
}
136136

@@ -259,7 +259,7 @@ macro_rules! impl_adc1234_trigger {
259259
pub fn enable_source<T: $trait_>(&mut self, _trigger: &T) {
260260
let common = unsafe { &*HRTIM_COMMON::ptr() };
261261
unsafe {
262-
common.$adcXr.modify(|r, w| w.bits(r.bits() | T::BITS));
262+
common.$adcXr().modify(|r, w| w.bits(r.bits() | T::BITS));
263263
}
264264
}
265265
}
@@ -288,8 +288,8 @@ macro_rules! impl_adc5678910_trigger {
288288
pub fn enable_source<T: $trait_>(&mut self, _trigger: &T) {
289289
let common = unsafe { &*HRTIM_COMMON::ptr() };
290290
common
291-
.adcer
292-
.modify(|_r, w| w.$adcXtrg().variant(T::BITS as u8));
291+
.adcer()
292+
.modify(|_r, w| unsafe { w.$adcXtrg().bits(T::BITS as u8) });
293293
}
294294
}
295295

‎src/hrtim/external_event.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ macro_rules! impl_eev1_5_to_es {
281281
// SAFETY: Thanks to, `HrTimCalibrated`, we know we have exclusive access to the register,
282282
// we also know no timers are started.
283283
unsafe {
284-
common.eecr1.modify(|_r, w| {
284+
common.eecr1().modify(|_r, w| {
285285
w.$eeXsrc()
286286
.bits(src_bits)
287287
.$eeXpol()
@@ -324,15 +324,15 @@ macro_rules! impl_eev6_10_to_es {
324324
// SAFETY: Thanks to, `HrTimCalibrated`, we know we have exclusive access to the register,
325325
// we also know no timers are started.
326326
unsafe {
327-
common.eecr2.modify(|_r, w| {
327+
common.eecr2().modify(|_r, w| {
328328
w.$eeXsrc()
329329
.bits(src_bits)
330330
.$eeXpol()
331331
.bit(polarity_bit)
332332
.$eeXsns()
333333
.bits(edge_or_polarity_bits)
334334
});
335-
common.eecr3.modify(|_r, w| w.$eeXf().bits(filter_bits));
335+
common.eecr3().modify(|_r, w| w.$eeXf().bits(filter_bits));
336336
}
337337

338338
ExternalEventSource { _x: PhantomData }

‎src/hrtim/fault.rs‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -115,16 +115,16 @@ macro_rules! impl_faults {
115115
unsafe {
116116
let common = &*HRTIM_COMMON::ptr();
117117

118-
common.fltinr2.modify(|_r, w| w.$fltWsrc_1().bit(src_bits & 0b10 != 0));
119-
common.$fltinrZ.modify(|_r, w| w
118+
common.fltinr2().modify(|_r, w| w.$fltWsrc_1().bit(src_bits & 0b10 != 0));
119+
common.$fltinrZ().modify(|_r, w| w
120120
.$fltWsrc_0().bit(src_bits & 0b01 != 0)
121121
.$fltWp().bit(is_active_high)
122122
.$fltWf().bits(filter_bits)
123123
.$fltWe().set_bit() // Enable
124124
);
125125

126126
// ... and lock configuration
127-
common.$fltinrZ.modify(|_r, w| w.$fltWlck().set_bit());
127+
common.$fltinrZ().modify(|_r, w| w.$fltWlck().set_bit());
128128
}
129129

130130
$source {
@@ -250,17 +250,17 @@ macro_rules! impl_flt_monitor {
250250
impl FaultMonitor for $t {
251251
fn enable_interrupt(&mut self, _hr_control: &mut HrPwmCtrl) {
252252
let common = unsafe { &*HRTIM_COMMON::ptr() };
253-
common.ier.modify(|_r, w| w.$fltxie().set_bit());
253+
common.ier().modify(|_r, w| w.$fltxie().set_bit());
254254
}
255255

256256
fn is_fault_active(&self) -> bool {
257257
let common = unsafe { &*HRTIM_COMMON::ptr() };
258-
common.isr.read().$fltx().bit()
258+
common.isr().read().$fltx().bit()
259259
}
260260

261261
fn clear_fault(&mut self) {
262262
let common = unsafe { &*HRTIM_COMMON::ptr() };
263-
common.icr.write(|w| w.$fltxc().set_bit());
263+
common.icr().write(|w| w.$fltxc().set_bit());
264264
}
265265
}
266266
)+};

‎src/hrtim/mod.rs‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ macro_rules! hrtim_finalize_body {
222222
};
223223

224224
// Write prescaler and any special modes
225-
tim.$timXcr.modify(|_r, w| unsafe {
225+
tim.$timXcr().modify(|_r, w| unsafe {
226226
w
227227
// Enable Continuous mode
228228
.cont().bit($this.timer_mode == HrTimerMode::Continuous)
@@ -241,27 +241,27 @@ macro_rules! hrtim_finalize_body {
241241
});
242242

243243
$(
244-
tim.$timXcr2.modify(|_r, w|
244+
tim.$timXcr2().modify(|_r, w|
245245
// Set counting direction
246246
w.udm().bit($this.counting_direction == HrCountingDirection::UpDown)
247247
);
248248

249249
// Only available for timers with outputs(not HRTIM_MASTER)
250-
let _ = tim.$outXr;
251-
tim.$timXcr.modify(|_r, w|
250+
let _ = tim.$outXr();
251+
tim.$timXcr().modify(|_r, w|
252252
// Push-Pull mode
253253
w.pshpll().bit($this.enable_push_pull)
254254
);
255255
)*
256256

257257
// Write period
258-
tim.$perXr.write(|w| unsafe { w.$perx().bits(period as u16) });
258+
tim.$perXr().write(|w| unsafe { w.$perx().bits(period as u16) });
259259

260260
// Enable fault sources and lock configuration
261261
$(unsafe {
262262
// Enable fault sources
263263
let fault_enable_bits = $this.fault_enable_bits as u32;
264-
tim.$fltXr.write(|w| w
264+
tim.$fltXr().write(|w| w
265265
.flt1en().bit(fault_enable_bits & (1 << 0) != 0)
266266
.flt2en().bit(fault_enable_bits & (1 << 1) != 0)
267267
.flt3en().bit(fault_enable_bits & (1 << 2) != 0)
@@ -271,9 +271,9 @@ macro_rules! hrtim_finalize_body {
271271
);
272272

273273
// ... and lock configuration
274-
tim.$fltXr.modify(|_r, w| w.fltlck().set_bit());
274+
tim.$fltXr().modify(|_r, w| w.fltlck().set_bit());
275275

276-
tim.$outXr.modify(|_r, w| w
276+
tim.$outXr().modify(|_r, w| w
277277
// Set actions on fault for both outputs
278278
.fault1().bits($this.fault1_bits)
279279
.fault2().bits($this.fault2_bits)
@@ -293,7 +293,7 @@ macro_rules! hrtim_finalize_body {
293293

294294
// SAFETY: DeadtimeConfig makes sure rising and falling values are valid
295295
// and DeadtimePrescaler has its own garantuee
296-
tim.$dtXr.modify(|_r, w| w
296+
tim.$dtXr().modify(|_r, w| w
297297
.dtprsc().bits(prescaler as u8)
298298
.dtrx().bits(deadtime_rising_value)
299299
.sdtrx().bit(deadtime_rising_sign)
@@ -306,26 +306,26 @@ macro_rules! hrtim_finalize_body {
306306
.dtrlkx().set_bit()
307307
.dtrslkx().set_bit()
308308
);
309-
tim.$outXr.modify(|_r, w| w.dten().set_bit());
309+
tim.$outXr().modify(|_r, w| w.dten().set_bit());
310310
}
311311

312312
// External event configs
313313
let eev_cfg = $this.eev_cfg.clone();
314-
tim.$eefXr1.write(|w| w
314+
tim.$eefXr1().write(|w| w
315315
.ee1ltch().bit(eev_cfg.eev1.latch_bit).ee1fltr().bits(eev_cfg.eev1.filter_bits)
316316
.ee2ltch().bit(eev_cfg.eev2.latch_bit).ee2fltr().bits(eev_cfg.eev2.filter_bits)
317317
.ee3ltch().bit(eev_cfg.eev3.latch_bit).ee3fltr().bits(eev_cfg.eev3.filter_bits)
318318
.ee4ltch().bit(eev_cfg.eev4.latch_bit).ee4fltr().bits(eev_cfg.eev4.filter_bits)
319319
.ee5ltch().bit(eev_cfg.eev5.latch_bit).ee5fltr().bits(eev_cfg.eev5.filter_bits)
320320
);
321-
tim.$eefXr2.write(|w| w
321+
tim.$eefXr2().write(|w| w
322322
.ee6ltch().bit(eev_cfg.eev6.latch_bit).ee6fltr().bits(eev_cfg.eev6.filter_bits)
323323
.ee7ltch().bit(eev_cfg.eev7.latch_bit).ee7fltr().bits(eev_cfg.eev7.filter_bits)
324324
.ee8ltch().bit(eev_cfg.eev8.latch_bit).ee8fltr().bits(eev_cfg.eev8.filter_bits)
325325
.ee9ltch().bit(eev_cfg.eev9.latch_bit).ee9fltr().bits(eev_cfg.eev9.filter_bits)
326326
.ee10ltch().bit(eev_cfg.eev10.latch_bit).ee10fltr().bits(eev_cfg.eev10.filter_bits)
327327
);
328-
tim.$Xeefr3.write(|w| w
328+
tim.$Xeefr3().write(|w| w
329329
.eevace().bit(eev_cfg.event_counter_enable_bit)
330330
// External Event A Counter Reset"]
331331
//.eevacres().bit()
@@ -339,10 +339,10 @@ macro_rules! hrtim_finalize_body {
339339
hrtim_finalize_body!($PreloadSource, $this, tim, $timXcr);
340340

341341
// Set repetition counter
342-
unsafe { tim.$rep.write(|w| w.$repx().bits($this.repetition_counter)); }
342+
unsafe { tim.$rep().write(|w| w.$repx().bits($this.repetition_counter)); }
343343

344344
// Enable interrupts
345-
tim.$dier.modify(|_r, w| w.$repie().bit($this.enable_repetition_interrupt));
345+
tim.$dier().modify(|_r, w| w.$repie().bit($this.enable_repetition_interrupt));
346346

347347
// Start timer
348348
//let master = unsafe { &*HRTIM_MASTER::ptr() };
@@ -359,19 +359,19 @@ macro_rules! hrtim_finalize_body {
359359
(PreloadSource, $this:expr, $tim:expr, $timXcr:ident) => {{
360360
match $this.preload_source {
361361
Some(PreloadSource::OnCounterReset) => {
362-
$tim.$timXcr.modify(|_r, w| w
362+
$tim.$timXcr().modify(|_r, w| w
363363
.tx_rstu().set_bit()
364364
.preen().set_bit()
365365
)
366366
},
367367
Some(PreloadSource::OnMasterTimerUpdate) => {
368-
$tim.$timXcr.modify(|_r, w| w
368+
$tim.$timXcr().modify(|_r, w| w
369369
.mstu().set_bit()
370370
.preen().set_bit()
371371
)
372372
}
373373
Some(PreloadSource::OnRepetitionUpdate) => {
374-
$tim.$timXcr.modify(|_r, w| w
374+
$tim.$timXcr().modify(|_r, w| w
375375
.tx_repu().set_bit()
376376
.preen().set_bit()
377377
)
@@ -383,7 +383,7 @@ macro_rules! hrtim_finalize_body {
383383
(MasterPreloadSource, $this:expr, $tim:expr, $timXcr:ident) => {{
384384
match $this.preload_source {
385385
Some(MasterPreloadSource::OnMasterRepetitionUpdate) => {
386-
$tim.$timXcr.modify(|_r, w| w
386+
$tim.$timXcr().modify(|_r, w| w
387387
.mrepu().set_bit()
388388
.preen().set_bit()
389389
)

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