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Update for new pac (#183)
* Changes from stm32g4-staging v0.19 to stm32-rs#1156 * Follow @burrbull suggestion * Use `clear` methods to clear interrupt flags * Bump pac * fmt * Fix i2c * Fix new clippy issues
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8 files changed

+61
-63
lines changed

8 files changed

+61
-63
lines changed

‎Cargo.toml

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,7 @@ version = "0.0.2"
1313

1414
[dependencies]
1515
nb = "1"
16-
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
17-
stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
16+
stm32g4 = { version = "0.21.0", package = "stm32g4-staging" }
1817
paste = "1.0"
1918
bitflags = "1.2"
2019
vcell = "0.1"

‎src/adc.rs

Lines changed: 9 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1662,14 +1662,14 @@ macro_rules! adc {
16621662
self.calibrate_all();
16631663
self.apply_config(self.config);
16641664

1665-
self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
1665+
self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
16661666
self.adc_reg.cr().modify(|_, w| w.aden().set_bit());
16671667

16681668
// Wait for adc to get ready
16691669
while !self.adc_reg.isr().read().adrdy().bit_is_set() {}
16701670

16711671
// Clear ready flag
1672-
self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
1672+
self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
16731673

16741674
self.clear_end_of_conversion_flag();
16751675
}
@@ -1839,26 +1839,11 @@ macro_rules! adc {
18391839
pub fn set_channel_input_type(&mut self, df: config::DifferentialSelection) {
18401840
self.config.difsel = df;
18411841

1842-
self.adc_reg.difsel().modify(|_, w| {w
1843-
.difsel_0().bit(df.get_channel(0).into() )
1844-
.difsel_1().bit(df.get_channel(1).into() )
1845-
.difsel_2().bit(df.get_channel(2).into() )
1846-
.difsel_3().bit(df.get_channel(3).into() )
1847-
.difsel_4().bit(df.get_channel(4).into() )
1848-
.difsel_5().bit(df.get_channel(5).into() )
1849-
.difsel_6().bit(df.get_channel(6).into() )
1850-
.difsel_7().bit(df.get_channel(7).into() )
1851-
.difsel_8().bit(df.get_channel(8).into() )
1852-
.difsel_9().bit(df.get_channel(9).into() )
1853-
.difsel_10().bit(df.get_channel(10).into() )
1854-
.difsel_11().bit(df.get_channel(11).into() )
1855-
.difsel_12().bit(df.get_channel(12).into() )
1856-
.difsel_13().bit(df.get_channel(13).into() )
1857-
.difsel_14().bit(df.get_channel(14).into() )
1858-
.difsel_15().bit(df.get_channel(15).into() )
1859-
.difsel_16().bit(df.get_channel(16).into() )
1860-
.difsel_17().bit(df.get_channel(17).into() )
1861-
.difsel_18().bit(df.get_channel(18).into() )
1842+
self.adc_reg.difsel().modify(|_, w| {
1843+
for i in 0..18 {
1844+
w.difsel(i).bit(df.get_channel(i).into());
1845+
}
1846+
w
18621847
});
18631848
}
18641849

@@ -2014,7 +1999,7 @@ macro_rules! adc {
20141999
/// Resets the end-of-conversion flag
20152000
#[inline(always)]
20162001
pub fn clear_end_of_conversion_flag(&mut self) {
2017-
self.adc_reg.isr().modify(|_, w| w.eoc().set_bit());
2002+
self.adc_reg.isr().modify(|_, w| w.eoc().clear());
20182003
}
20192004

20202005
/// Block until the conversion is completed and return to configured
@@ -2123,7 +2108,7 @@ macro_rules! adc {
21232108
/// Resets the overrun flag
21242109
#[inline(always)]
21252110
pub fn clear_overrun_flag(&mut self) {
2126-
self.adc_reg.isr().modify(|_, w| w.ovr().set_bit());
2111+
self.adc_reg.isr().modify(|_, w| w.ovr().clear());
21272112
}
21282113
}
21292114

‎src/dma/channel.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -91,9 +91,9 @@ pub trait DMAExt<I> {
9191
impl DMAExt<Self> for DMA1 {
9292
fn split(self, rcc: &Rcc) -> Channels<DMA1> {
9393
// Enable DMAMux is not yet enabled
94-
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
94+
if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
9595
// Enable peripheral
96-
rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
96+
rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
9797
}
9898

9999
// Enable peripheral
@@ -106,9 +106,9 @@ impl DMAExt<Self> for DMA1 {
106106
impl DMAExt<Self> for DMA2 {
107107
fn split(self, rcc: &Rcc) -> Channels<DMA2> {
108108
// Enable DMAMux is not yet enabled
109-
if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
109+
if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
110110
// Enable peripheral
111-
rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
111+
rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
112112
}
113113

114114
// Enable peripheral

‎src/exti.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -109,10 +109,10 @@ impl ExtiExt for EXTI {
109109
match ev as u8 {
110110
line if line < 32 => self
111111
.imr1()
112-
.modify(|r, w| unsafe { w.bits(r.bits() | 1 << line) }),
112+
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << line)) }),
113113
line => self
114114
.imr2()
115-
.modify(|r, w| unsafe { w.bits(r.bits() | 1 << (line - 32)) }),
115+
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (line - 32))) }),
116116
};
117117
}
118118

‎src/flash.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -288,14 +288,14 @@ impl<const SECTOR_SZ_KB: u32> FlashWriter<'_, SECTOR_SZ_KB> {
288288
word2 = (tmp_dword >> 32) as u32;
289289
} else {
290290
word1 = (data[idx] as u32)
291-
| (data[idx + 1] as u32) << 8
292-
| (data[idx + 2] as u32) << 16
293-
| (data[idx + 3] as u32) << 24;
291+
| ((data[idx + 1] as u32) << 8)
292+
| ((data[idx + 2] as u32) << 16)
293+
| ((data[idx + 3] as u32) << 24);
294294

295295
word2 = (data[idx + 4] as u32)
296-
| (data[idx + 5] as u32) << 8
297-
| (data[idx + 6] as u32) << 16
298-
| (data[idx + 7] as u32) << 24;
296+
| ((data[idx + 5] as u32) << 8)
297+
| ((data[idx + 6] as u32) << 16)
298+
| ((data[idx + 7] as u32) << 24);
299299
}
300300

301301
// Set Page Programming to 1

‎src/i2c.rs

Lines changed: 33 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
//! I2C
2+
use crate::stm32::i2c1;
23
use embedded_hal::i2c::{ErrorKind, Operation, SevenBitAddress, TenBitAddress};
34
use embedded_hal_old::blocking::i2c::{Read, Write, WriteRead};
45

@@ -24,8 +25,11 @@ use crate::stm32::I2C4;
2425
use crate::stm32::{I2C1, I2C2, I2C3, RCC};
2526
use crate::time::Hertz;
2627
use core::cmp;
28+
use core::convert::TryInto;
2729

2830
/// I2C bus configuration.
31+
#[derive(Debug, Clone, Copy)]
32+
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
2933
pub struct Config {
3034
speed: Option<Hertz>,
3135
timing: Option<u32>,
@@ -79,9 +83,13 @@ impl Config {
7983
self
8084
}
8185

82-
fn timing_bits(&self, i2c_clk: Hertz) -> u32 {
86+
fn timing_bits(
87+
self,
88+
i2c_clk: Hertz,
89+
reg: &mut stm32g4::raw::W<i2c1::timingr::TIMINGRrs>,
90+
) -> &mut stm32g4::raw::W<i2c1::timingr::TIMINGRrs> {
8391
if let Some(bits) = self.timing {
84-
return bits;
92+
return unsafe { reg.bits(bits) };
8593
}
8694
let speed = self.speed.unwrap();
8795
let (psc, scll, sclh, sdadel, scldel) = if speed.raw() <= 100_000 {
@@ -99,7 +107,17 @@ impl Config {
99107
let scldel = 3;
100108
(psc, scll, sclh, sdadel, scldel)
101109
};
102-
psc << 28 | scldel << 20 | sdadel << 16 | sclh << 8 | scll
110+
111+
reg.presc()
112+
.set(psc.try_into().unwrap())
113+
.scldel()
114+
.set(scldel)
115+
.sdadel()
116+
.set(sdadel)
117+
.sclh()
118+
.set(sclh.try_into().unwrap())
119+
.scll()
120+
.set(scll.try_into().unwrap())
103121
}
104122
}
105123

@@ -172,14 +190,13 @@ macro_rules! busy_wait {
172190
if isr.$flag().$variant() {
173191
break;
174192
} else if isr.berr().bit_is_set() {
175-
$i2c.icr().write(|w| w.berrcf().set_bit());
193+
$i2c.icr().write(|w| w.berrcf().clear());
176194
return Err(Error::BusError);
177195
} else if isr.arlo().bit_is_set() {
178-
$i2c.icr().write(|w| w.arlocf().set_bit());
196+
$i2c.icr().write(|w| w.arlocf().clear());
179197
return Err(Error::ArbitrationLost);
180198
} else if isr.nackf().bit_is_set() {
181-
$i2c.icr()
182-
.write(|w| w.stopcf().set_bit().nackcf().set_bit());
199+
$i2c.icr().write(|w| w.stopcf().clear().nackcf().clear());
183200
flush_txdr!($i2c);
184201
return Err(Error::Nack);
185202
} else {
@@ -241,20 +258,17 @@ macro_rules! i2c {
241258
i2c.cr1().modify(|_, w| w.pe().clear_bit());
242259

243260
// Setup protocol timings
244-
let timing_bits = config.timing_bits(<$I2CX as RccBus>::Bus::get_frequency(&rcc.clocks));
245-
i2c.timingr().write(|w| unsafe { w.bits(timing_bits) });
261+
i2c.timingr().write(|w| config.timing_bits(<$I2CX as RccBus>::Bus::get_frequency(&rcc.clocks), w));
246262

247263
// Enable the I2C processing
248-
unsafe {
249-
i2c.cr1().modify(|_, w| {
250-
w.pe()
251-
.set_bit()
252-
.dnf()
253-
.bits(config.digital_filter)
254-
.anfoff()
255-
.bit(!config.analog_filter)
256-
});
257-
}
264+
i2c.cr1().modify(|_, w| {
265+
w.pe()
266+
.set_bit()
267+
.dnf()
268+
.set(config.digital_filter)
269+
.anfoff()
270+
.bit(!config.analog_filter)
271+
});
258272

259273
I2c { i2c, sda, scl }
260274
}

‎src/rcc/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -457,7 +457,7 @@ impl Rcc {
457457
let csr = self.rb.csr().read();
458458

459459
ResetReason {
460-
low_power: csr.lpwrstf().bit(),
460+
low_power: csr.lpwrrstf().bit(),
461461
window_watchdog: csr.wwdgrstf().bit(),
462462
independent_watchdog: csr.iwdgrstf().bit(),
463463
software: csr.sftrstf().bit(),

‎src/serial/usart.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -221,16 +221,16 @@ macro_rules! uart_shared {
221221
let isr = usart.isr().read();
222222
Err(
223223
if isr.pe().bit_is_set() {
224-
usart.icr().write(|w| w.pecf().set_bit());
224+
usart.icr().write(|w| w.pecf().clear());
225225
nb::Error::Other(Error::Parity)
226226
} else if isr.fe().bit_is_set() {
227-
usart.icr().write(|w| w.fecf().set_bit());
227+
usart.icr().write(|w| w.fecf().clear());
228228
nb::Error::Other(Error::Framing)
229229
} else if isr.nf().bit_is_set() {
230-
usart.icr().write(|w| w.ncf().set_bit());
230+
usart.icr().write(|w| w.ncf().clear());
231231
nb::Error::Other(Error::Noise)
232232
} else if isr.ore().bit_is_set() {
233-
usart.icr().write(|w| w.orecf().set_bit());
233+
usart.icr().write(|w| w.orecf().clear());
234234
nb::Error::Other(Error::Overrun)
235235
} else if isr.rxne().bit_is_set() {
236236
return Ok(())
@@ -827,7 +827,7 @@ macro_rules! uart_full {
827827
/// Clear pending receiver timeout interrupt
828828
pub fn clear_timeout(&mut self) {
829829
let usart = unsafe { &(*$USARTX::ptr()) };
830-
usart.icr().write(|w| w.rtocf().set_bit());
830+
usart.icr().write(|w| w.rtocf().clear());
831831
}
832832
}
833833
};

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