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usbalbinusbalbin
committed
Update for new pac
1 parent c69fa32 commit b4c460e

21 files changed

+564
-560
lines changed

‎examples/flash_with_rtic.rs

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ mod app {
1212
use crate::utils::logger;
1313
use stm32g4xx_hal::flash::{FlashExt, FlashSize, FlashWriter, Parts};
1414
use stm32g4xx_hal::prelude::*;
15+
use stm32g4xx_hal::pwr::PwrExt;
1516
use stm32g4xx_hal::rcc::{PllConfig, RccExt};
1617

1718
const LOG_LEVEL: log::LevelFilter = log::LevelFilter::Info;
@@ -67,11 +68,12 @@ mod app {
6768
// The ADC will ultimately be put into synchronous mode and will derive
6869
// its clock from the AHB bus clock, with a prescalar of 2 or 4.
6970

70-
let mut rcc = rcc.freeze(clock_config);
71+
let pwr = dp.PWR.constrain().freeze();
72+
let mut rcc = rcc.freeze(clock_config, pwr);
7173

7274
unsafe {
7375
let mut flash = &(*stm32g4xx_hal::stm32::FLASH::ptr());
74-
flash.acr.modify(|_, w| {
76+
flash.acr().modify(|_, w| {
7577
w.latency().bits(0b1000) // 8 wait states
7678
});
7779
}

‎src/adc.rs

Lines changed: 97 additions & 97 deletions
Large diffs are not rendered by default.

‎src/can.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,9 @@ where
5555
{
5656
Self::enable(&rcc.rb);
5757

58-
if rcc.rb.ccipr.read().fdcansel().is_hse() {
58+
if rcc.rb.ccipr().read().fdcansel().is_hse() {
5959
// Select P clock as FDCAN clock source
60-
rcc.rb.ccipr.modify(|_, w| {
60+
rcc.rb.ccipr().modify(|_, w| {
6161
// This is sound, as `FdCanClockSource` only contains valid values for this field.
6262
unsafe {
6363
w.fdcansel().bits(FdCanClockSource::PCLK as u8);

‎src/comparator.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ macro_rules! impl_comp {
6464
pub fn csr(&self) -> &$crate::stm32::comp::$reg_t {
6565
// SAFETY: The COMP1 type is only constructed with logical ownership of
6666
// these registers.
67-
&unsafe { &*COMP::ptr() }.$reg
67+
&unsafe { &*COMP::ptr() }.$reg()
6868
}
6969
}
7070
)+};
@@ -541,11 +541,11 @@ type Comparators = (COMP1, COMP2, COMP3, COMP4, COMP5, COMP6, COMP7);
541541
/// Enables the comparator peripheral, and splits the [`COMP`] into independent [`COMP1`] and [`COMP2`]
542542
pub fn split(_comp: COMP, rcc: &mut Rcc) -> Comparators {
543543
// Enable COMP, SYSCFG, VREFBUF clocks
544-
rcc.rb.apb2enr.modify(|_, w| w.syscfgen().set_bit());
544+
rcc.rb.apb2enr().modify(|_, w| w.syscfgen().set_bit());
545545

546546
// Reset COMP, SYSCFG, VREFBUF
547-
rcc.rb.apb2rstr.modify(|_, w| w.syscfgrst().set_bit());
548-
rcc.rb.apb2rstr.modify(|_, w| w.syscfgrst().clear_bit());
547+
rcc.rb.apb2rstr().modify(|_, w| w.syscfgrst().set_bit());
548+
rcc.rb.apb2rstr().modify(|_, w| w.syscfgrst().clear_bit());
549549

550550
(
551551
COMP1 { _rb: PhantomData },

‎src/dac.rs

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -193,8 +193,8 @@ macro_rules! dac_helper {
193193
pub fn enable(self) -> $CX<MODE_BITS, Enabled> {
194194
let dac = unsafe { &(*<$DAC>::ptr()) };
195195

196-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
197-
dac.dac_cr.modify(|_, w| w.$en().set_bit());
196+
dac.dac_mcr().modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
197+
dac.dac_cr().modify(|_, w| w.$en().set_bit());
198198

199199
$CX {
200200
_enabled: PhantomData,
@@ -204,8 +204,8 @@ macro_rules! dac_helper {
204204
pub fn enable_generator(self, config: GeneratorConfig) -> $CX<MODE_BITS, WaveGenerator> {
205205
let dac = unsafe { &(*<$DAC>::ptr()) };
206206

207-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
208-
dac.dac_cr.modify(|_, w| unsafe {
207+
dac.dac_mcr().modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
208+
dac.dac_cr().modify(|_, w| unsafe {
209209
w.$wave().bits(config.mode);
210210
w.$ten().set_bit();
211211
w.$mamp().bits(config.amp);
@@ -235,19 +235,19 @@ macro_rules! dac_helper {
235235
T: DelayUs<u32>,
236236
{
237237
let dac = unsafe { &(*<$DAC>::ptr()) };
238-
dac.dac_cr.modify(|_, w| w.$en().clear_bit());
239-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
240-
dac.dac_cr.modify(|_, w| w.$cen().set_bit());
238+
dac.dac_cr().modify(|_, w| w.$en().clear_bit());
239+
dac.dac_mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
240+
dac.dac_cr().modify(|_, w| w.$cen().set_bit());
241241
let mut trim = 0;
242242
while true {
243-
dac.dac_ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
243+
dac.dac_ccr().modify(|_, w| unsafe { w.$trim().bits(trim) });
244244
delay.delay_us(64_u32);
245-
if dac.dac_sr.read().$cal_flag().bit() {
245+
if dac.dac_sr().read().$cal_flag().bit() {
246246
break;
247247
}
248248
trim += 1;
249249
}
250-
dac.dac_cr.modify(|_, w| w.$cen().clear_bit());
250+
dac.dac_cr().modify(|_, w| w.$cen().clear_bit());
251251

252252
$CX {
253253
_enabled: PhantomData,
@@ -257,7 +257,7 @@ macro_rules! dac_helper {
257257
/// Disable the DAC channel
258258
pub fn disable(self) -> $CX<MODE_BITS, Disabled> {
259259
let dac = unsafe { &(*<$DAC>::ptr()) };
260-
dac.dac_cr.modify(|_, w| unsafe {
260+
dac.dac_cr().modify(|_, w| unsafe {
261261
w.$en().clear_bit().$wave().bits(0).$ten().clear_bit()
262262
});
263263

@@ -272,20 +272,20 @@ macro_rules! dac_helper {
272272
impl<const MODE_BITS: u8, ED> DacOut<u16> for $CX<MODE_BITS, ED> {
273273
fn set_value(&mut self, val: u16) {
274274
let dac = unsafe { &(*<$DAC>::ptr()) };
275-
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
275+
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
276276
}
277277

278278
fn get_value(&mut self) -> u16 {
279279
let dac = unsafe { &(*<$DAC>::ptr()) };
280-
dac.$dac_dor.read().bits() as u16
280+
dac.$dac_dor().read().bits() as u16
281281
}
282282
}
283283

284284
/// Wave generator state implementation
285285
impl<const MODE_BITS: u8> $CX<MODE_BITS, WaveGenerator> {
286286
pub fn trigger(&mut self) {
287287
let dac = unsafe { &(*<$DAC>::ptr()) };
288-
dac.dac_swtrgr.write(|w| { w.$swtrig().set_bit() });
288+
dac.dac_swtrgr().write(|w| { w.$swtrig().set_bit() });
289289
}
290290
}
291291
)+

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