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lines changed Original file line number Diff line number Diff line change @@ -379,8 +379,11 @@ impl Rcc {
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// The sequence to switch from Range11 normal mode to Range1 boost mode is:
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// 1. The system clock must be divided by 2 using the AHB prescaler before switching to a
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// higher system frequency.
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- self . rb . cfgr . modify ( |_, w| unsafe { w. hpre ( ) . bits ( 0b1000 ) } ) ;
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- while self . rb . cfgr . read ( ) . hpre ( ) . bits ( ) != 0b1000 { }
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+ let half_apb = ( self . rb . cfgr . read ( ) . hpre ( ) . bits ( ) + 1 ) . clamp ( 0b1000 , 0b1111 ) ;
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+ self . rb
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+ . cfgr
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+ . modify ( |_r, w| unsafe { w. hpre ( ) . bits ( half_apb) } ) ;
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+ while self . rb . cfgr . read ( ) . hpre ( ) . bits ( ) != half_apb { }
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// 2. Clear the R1MODE bit is in the PWR_CR5 register.
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unsafe { pwr:: set_boost ( true ) } ;
@@ -402,8 +405,12 @@ impl Rcc {
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// 5. Wait for at least 1us and then reconfigure the AHB prescaler to get the needed HCLK
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// clock frequency.
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+ let us_per_s = 1_000_000 ;
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+ // Number of cycles @ sys_freq for 1us, rounded up, this will
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+ // likely end up being 2us since the AHB prescaler is changed
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+ let delay_cycles = ( sys_freq + us_per_s - 1 ) / us_per_s;
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+ cortex_m:: asm:: delay ( delay_cycles) ;
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- // TODO: Do we really need to wait another 1us or is that included in the wait loop in step 1?
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self . rb
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. cfgr
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. modify ( |_, w| unsafe { w. hpre ( ) . bits ( ahb_psc_bits) } ) ;
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