Fix SysCfg hardfault

The `SysCfg` peripheral used bit banding to set the APB2 peripheral clock enable bit which fails on an assertion on a G431KBT (have not tested on other chips, but I suspect they would do the same). This takes a mutable reference to `Rcc` in `SysCfg::constrain` and uses safe accessors to enable the clock.

Updated and tested the button example which is all that uses SysCfg.

```[INFO ] Configuring PLL (stm32_foc stm32-foc/src/main.rs:132)
[INFO ] System clock frequency: 168000000 (stm32_foc stm32-foc/src/main.rs:138)
[DEBUG] Write 20007FB0 (stm32g4xx_hal stm32g4xx-hal/src/bb.rs:42)
[ERROR] panicked at /Users/fuzz/wave/stm32g4xx-hal/src/bb.rs:44:5:
assertion failed: (PERI_ADDRESS_START..=PERI_ADDRESS_END).contains(&addr) (panic_probe panic-probe-1.0.0/src/lib.rs:104)
Firmware exited unexpectedly: Multiple
Core 0
    Frame 0: HardFault_ @ 0x08006394
       /Users/fuzz/.cargo/registry/src/index.crates.io-1949cf8c6b5b557f/cortex-m-rt-0.7.5/src/lib.rs:1103:1
    Frame 1: HardFault <Cause: Escalated UsageFault <Cause: Undefined instruction>> @ 0x08005ce2```

Author: boondocklabs

Embed.toml

@@ -0,0 +1,2 @@
+[default.rtt]
+enabled = true

examples/button.rs

@@ -53,7 +53,7 @@ fn main() -> ! {
 
     let mut dp = stm32::Peripherals::take().expect("cannot take peripherals");
     let mut rcc = dp.RCC.constrain();
-    let mut syscfg = dp.SYSCFG.constrain();
+    let mut syscfg = dp.SYSCFG.constrain(&mut rcc);
 
     println!("Led Init");
     // Configure PA5 pin to blink LED
@@ -80,7 +80,7 @@ fn main() -> ! {
 
     println!("Start Loop");
     loop {
-        wfi();
+        //wfi();
         println!("Check");
 
         if G_LED_ON.load(Ordering::Relaxed) {

src/syscfg.rs

@@ -1,25 +1,17 @@
-use crate::bb;
-use crate::stm32::{RCC, SYSCFG};
+use crate::rcc::Rcc;
+use crate::stm32::SYSCFG;
 use core::ops::Deref;
 
 /// Extension trait that constrains the `SYSCFG` peripheral
 pub trait SysCfgExt {
     /// Constrains the `SYSCFG` peripheral so it plays nicely with the other abstractions
-    fn constrain(self) -> SysCfg;
+    fn constrain(self, rcc: &mut Rcc) -> SysCfg;
 }
 
 impl SysCfgExt for SYSCFG {
-    fn constrain(self) -> SysCfg {
-        unsafe {
-            // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
-            let rcc = &(*RCC::ptr());
-
-            // Enable clock.
-            bb::set(&rcc.apb2enr(), 0);
-
-            // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
-            cortex_m::asm::dsb();
-        }
+    fn constrain(self, rcc: &mut Rcc) -> SysCfg {
+        // Enable SYSCFG peripheral clock in APB2ENR register
+        rcc.apb2enr().modify(|_, w| w.syscfgen().set_bit());
 
         SysCfg(self)
     }