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techmccatusbalbin
techmccat
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usbalbin
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spi demacro part 2
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+25
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‎src/spi.rs

Lines changed: 25 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ use crate::rcc::{Enable, GetBusFreq, Rcc, Reset};
1212
use crate::stm32::SPI4;
1313
use crate::stm32::{spi1, SPI1, SPI2, SPI3};
1414
use crate::time::Hertz;
15-
use core::ptr;
15+
use core::{ptr, ops::Deref};
1616

1717
use embedded_hal::spi::ErrorKind;
1818
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
@@ -87,17 +87,21 @@ impl FrameSize for u16 {
8787

8888
pub trait Instance:
8989
crate::Sealed
90-
// everything derefs to spi4, except spi1
91-
// + Deref<Target = crate::stm32::spi1::RegisterBlock>
90+
+ Deref<Target = spi1::RegisterBlock>
9291
+ Enable
9392
+ Reset
9493
+ GetBusFreq
9594
{
96-
const PTR: *const spi1::RegisterBlock;
97-
#[inline]
98-
fn registers(&self) -> &spi1::RegisterBlock {
99-
unsafe { &*Self::PTR }
95+
const DMA_MUX_RESOURCE: DmaMuxResources;
96+
}
97+
98+
unsafe impl<SPI: Instance, PINS> TargetAddress<MemoryToPeripheral> for Spi<SPI, PINS> {
99+
#[inline(always)]
100+
fn address(&self) -> u32 {
101+
self.spi.dr() as *const _ as u32
100102
}
103+
type MemSize = u8;
104+
const REQUEST_LINE: Option<u8> = Some(SPI::DMA_MUX_RESOURCE as u8);
101105
}
102106

103107
macro_rules! spi {
@@ -125,17 +129,7 @@ macro_rules! spi {
125129
)*
126130

127131
impl Instance for $SPIX {
128-
const PTR: *const crate::stm32::spi1::RegisterBlock = $SPIX::PTR as *const crate::stm32::spi1::RegisterBlock;
129-
}
130-
131-
unsafe impl<PINS> TargetAddress<MemoryToPeripheral> for Spi<$SPIX, PINS> {
132-
#[inline(always)]
133-
fn address(&self) -> u32 {
134-
// unsafe: only the Tx part accesses the Tx register
135-
unsafe { &*<$SPIX>::ptr() }.dr() as *const _ as u32
136-
}
137-
type MemSize = u8;
138-
const REQUEST_LINE: Option<u8> = Some($mux as u8);
132+
const DMA_MUX_RESOURCE: DmaMuxResources = $mux;
139133
}
140134
}
141135
}
@@ -147,7 +141,6 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
147141

148142
pub fn enable_tx_dma(self) -> Spi<SPI, PINS> {
149143
self.spi
150-
.registers()
151144
.cr2()
152145
.modify(|_, w| w.txdmaen().set_bit());
153146
Spi {
@@ -158,7 +151,7 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
158151

159152
#[inline]
160153
fn nb_read<W: FrameSize>(&mut self) -> nb::Result<W, Error> {
161-
let sr = self.spi.registers().sr().read();
154+
let sr = self.spi.sr().read();
162155
Err(if sr.ovr().bit_is_set() {
163156
nb::Error::Other(Error::Overrun)
164157
} else if sr.modf().bit_is_set() {
@@ -173,7 +166,7 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
173166
}
174167
#[inline]
175168
fn nb_write<W: FrameSize>(&mut self, word: W) -> nb::Result<(), Error> {
176-
let sr = self.spi.registers().sr().read();
169+
let sr = self.spi.sr().read();
177170
Err(if sr.ovr().bit_is_set() {
178171
nb::Error::Other(Error::Overrun)
179172
} else if sr.modf().bit_is_set() {
@@ -189,7 +182,7 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
189182
}
190183
#[inline]
191184
fn nb_read_no_err<W: FrameSize>(&mut self) -> nb::Result<W, core::convert::Infallible> {
192-
if self.spi.registers().sr().read().rxne().bit_is_set() {
185+
if self.spi.sr().read().rxne().bit_is_set() {
193186
Ok(self.read_unchecked())
194187
} else {
195188
Err(nb::Error::WouldBlock)
@@ -199,29 +192,28 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
199192
fn read_unchecked<W: FrameSize>(&mut self) -> W {
200193
// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
201194
// reading a half-word)
202-
unsafe { ptr::read_volatile(&self.spi.registers().dr() as *const _ as *const W) }
195+
unsafe { ptr::read_volatile(&self.spi.dr() as *const _ as *const W) }
203196
}
204197
#[inline]
205198
fn write_unchecked<W: FrameSize>(&mut self, word: W) {
206-
let dr = self.spi.registers().dr().as_ptr() as *mut W;
199+
// NOTE(write_volatile) see note above
200+
let dr = self.spi.dr().as_ptr() as *mut W;
207201
unsafe { ptr::write_volatile(dr, word) };
208202
}
209203
#[inline]
210204
pub fn set_tx_only(&mut self) {
211205
self.spi
212-
.registers()
213206
.cr1()
214207
.modify(|_, w| w.bidimode().set_bit().bidioe().set_bit());
215208
}
216209
#[inline]
217210
pub fn set_bidi(&mut self) {
218211
self.spi
219-
.registers()
220212
.cr1()
221213
.modify(|_, w| w.bidimode().clear_bit().bidioe().clear_bit());
222214
}
223215
fn tx_fifo_cap(&self) -> u8 {
224-
match self.spi.registers().sr().read().ftlvl().bits() {
216+
match self.spi.sr().read().ftlvl().bits() {
225217
0 => 4,
226218
1 => 3,
227219
2 => 2,
@@ -231,7 +223,7 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
231223
fn flush_inner(&mut self) -> Result<(), Error> {
232224
// stop receiving data
233225
self.set_tx_only();
234-
self.spi.registers().cr2().modify(|_, w| w.frxth().set_bit());
226+
self.spi.cr2().modify(|_, w| w.frxth().set_bit());
235227
// drain rx fifo
236228
while match self.nb_read::<u8>() {
237229
Ok(_) => true,
@@ -241,7 +233,7 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
241233
core::hint::spin_loop()
242234
}
243235
// wait for idle
244-
Ok(while self.spi.registers().sr().read().bsy().bit() {
236+
Ok(while self.spi.sr().read().bsy().bit() {
245237
core::hint::spin_loop()
246238
})
247239
}
@@ -303,7 +295,7 @@ impl<SPI: Instance> SpiExt<SPI> for SPI {
303295

304296
let spi_freq = freq.into().raw();
305297
let bus_freq = SPI::get_frequency(&rcc.clocks).raw();
306-
setup_spi_regs(self.registers(), spi_freq, bus_freq, mode);
298+
setup_spi_regs(&self, spi_freq, bus_freq, mode);
307299

308300
Spi { spi: self, pins }
309301
}
@@ -324,7 +316,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
324316
self.flush_inner()?;
325317
// FIFO threshold to 16 bits
326318
self.spi
327-
.registers()
328319
.cr2()
329320
.modify(|_, w| w.frxth().clear_bit());
330321
self.set_bidi();
@@ -349,7 +340,7 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
349340

350341
let odd_idx = len.saturating_sub(2 * prefill + pair_left);
351342
// FIFO threshold to 8 bits
352-
self.spi.registers().cr2().modify(|_, w| w.frxth().set_bit());
343+
self.spi.cr2().modify(|_, w| w.frxth().set_bit());
353344
if pair_left == 1 {
354345
nb::block!(self.nb_write(0u8))?;
355346
words[odd_idx] = nb::block!(self.nb_read_no_err()).unwrap();
@@ -389,7 +380,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
389380

390381
// FIFO threshold to 16 bits
391382
self.spi
392-
.registers()
393383
.cr2()
394384
.modify(|_, w| w.frxth().clear_bit());
395385

@@ -414,7 +404,7 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
414404
}
415405

416406
// FIFO threshold to 8 bits
417-
self.spi.registers().cr2().modify(|_, w| w.frxth().set_bit());
407+
self.spi.cr2().modify(|_, w| w.frxth().set_bit());
418408

419409
if pair_left == 1 {
420410
let write_idx = common_len - 1;
@@ -448,7 +438,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
448438
self.flush_inner()?;
449439
self.set_bidi();
450440
self.spi
451-
.registers()
452441
.cr2()
453442
.modify(|_, w| w.frxth().clear_bit());
454443
let half_len = len / 2;
@@ -471,7 +460,7 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u8> for Spi<SPI,
471460
let write = u16::from_le_bytes(words_alias[i + prefill]);
472461
nb::block!(self.nb_write(write))?;
473462
}
474-
self.spi.registers().cr2().modify(|_, w| w.frxth().set_bit());
463+
self.spi.cr2().modify(|_, w| w.frxth().set_bit());
475464

476465
if pair_left == 1 {
477466
let read_idx = len - 2 * prefill - 1;
@@ -503,7 +492,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u16> for Spi<SPI,
503492
self.flush_inner()?;
504493
// FIFO threshold to 16 bits
505494
self.spi
506-
.registers()
507495
.cr2()
508496
.modify(|_, w| w.frxth().clear_bit());
509497
self.set_bidi();
@@ -537,7 +525,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u16> for Spi<SPI,
537525
self.flush_inner()?;
538526
// FIFO threshold to 16 bits
539527
self.spi
540-
.registers()
541528
.cr2()
542529
.modify(|_, w| w.frxth().clear_bit());
543530
self.set_bidi();
@@ -575,7 +562,6 @@ impl<SPI: Instance, PINS: Pins<SPI>> embedded_hal::spi::SpiBus<u16> for Spi<SPI,
575562
self.flush_inner()?;
576563
self.set_bidi();
577564
self.spi
578-
.registers()
579565
.cr2()
580566
.modify(|_, w| w.frxth().clear_bit());
581567
let prefill = core::cmp::min(self.tx_fifo_cap() as usize / 2, len);

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