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Merge remote-tracking branch 'upstream/main' into update_for_main_changes
2 parents 46d44d8 + 4a69b88 commit efc5913

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5 files changed

+68
-216
lines changed

5 files changed

+68
-216
lines changed

‎examples/flash_with_rtic.rs

Lines changed: 40 additions & 189 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,14 @@ mod app {
8888
0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC,
8989
0xDE, 0xF0 as u8,
9090
];
91+
let data = [
92+
&one_byte[..],
93+
&two_bytes[..],
94+
&three_bytes[..],
95+
&four_bytes[..],
96+
&eight_bytes[..],
97+
&sixteen_bytes[..],
98+
];
9199
let mut flash = dp.FLASH.constrain();
92100
let mut flash_writer = flash.writer::<2048>(FlashSize::Sz256K);
93101

@@ -102,197 +110,40 @@ mod app {
102110
.erase(FLASH_EXAMPLE_START_ADDRESS, 128)
103111
.unwrap(); // Erase entire page
104112

105-
for i in 0..6 {
106-
match i {
107-
0 => {
108-
// This test should fail, as the data needs to be divisible by 8 and force padding is false
109-
let result = flash_writer.write(
110-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
111-
&one_byte,
112-
false,
113-
);
114-
assert!(result.is_err());
115-
assert_eq!(
116-
result.err().unwrap(),
117-
stm32g4xx_hal::flash::Error::ArrayMustBeDivisibleBy8
118-
);
119-
120-
// This test should pass, as the data needs to be divisible by 8 and force padding is true, so the one_byte array will be padded with 7 bytes of 0xFF
121-
let result = flash_writer.write(
122-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
123-
&one_byte,
124-
true,
125-
);
126-
assert!(result.is_ok());
127-
logger::info!(
128-
"Wrote 1 byte to address {}",
129-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
130-
);
131-
}
132-
1 => {
133-
// This test should fail, as the data needs to be divisible by 8 and force padding is false
134-
let result = flash_writer.write(
135-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
136-
&two_bytes,
137-
false,
138-
);
139-
assert!(result.is_err());
140-
assert_eq!(
141-
result.err().unwrap(),
142-
stm32g4xx_hal::flash::Error::ArrayMustBeDivisibleBy8
143-
);
144-
145-
// This test should pass, as the data needs to be divisible by 8 and force padding is true, so the one_byte array will be padded with 7 bytes of 0xFF
146-
let result = flash_writer.write(
147-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
148-
&two_bytes,
149-
true,
150-
);
151-
assert!(result.is_ok());
152-
logger::info!(
153-
"Wrote 2 bytes to address {}",
154-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
155-
);
156-
}
157-
2 => {
158-
// This test should fail, as the data needs to be divisible by 8 and force padding is false
159-
let result = flash_writer.write(
160-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
161-
&three_bytes,
162-
false,
163-
);
164-
assert!(result.is_err());
165-
assert_eq!(
166-
result.err().unwrap(),
167-
stm32g4xx_hal::flash::Error::ArrayMustBeDivisibleBy8
168-
);
169-
170-
// This test should pass, as the data needs to be divisible by 8 and force padding is true, so the one_byte array will be padded with 7 bytes of 0xFF
171-
let result = flash_writer.write(
172-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
173-
&three_bytes,
174-
true,
175-
);
176-
assert!(result.is_ok());
177-
logger::info!(
178-
"Wrote 3 bytes to address {}",
179-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
180-
);
181-
}
182-
3 => {
183-
// This test should fail, as the data needs to be divisible by 8 and force padding is false
184-
let result = flash_writer.write(
185-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
186-
&four_bytes,
187-
false,
188-
);
189-
assert!(result.is_err());
190-
assert_eq!(
191-
result.err().unwrap(),
192-
stm32g4xx_hal::flash::Error::ArrayMustBeDivisibleBy8
193-
);
194-
195-
// This test should pass, as the data needs to be divisible by 8 and force padding is true, so the one_byte array will be padded with 7 bytes of 0xFF
196-
let result = flash_writer.write(
197-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
198-
&four_bytes,
199-
true,
200-
);
201-
assert!(result.is_ok());
202-
logger::info!(
203-
"Wrote 4 bytes to address {}",
204-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
205-
);
206-
}
207-
4 => {
208-
flash_writer
209-
.write(
210-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
211-
&eight_bytes,
212-
false,
213-
)
214-
.unwrap();
215-
logger::info!(
216-
"Wrote 8 bytes to address {}",
217-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
218-
);
219-
}
220-
5 => {
221-
flash_writer
222-
.write(FLASH_EXAMPLE_START_ADDRESS + i * 16, &sixteen_bytes, false)
223-
.unwrap();
224-
logger::info!(
225-
"Wrote 16 bytes to address {}",
226-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
227-
);
228-
}
229-
_ => (),
230-
}
113+
for (i, data) in data.iter().enumerate() {
114+
let i = i as u32;
115+
// This test should fail, as the data needs to be divisible by 8 and force padding is false
116+
let result =
117+
flash_writer.write(FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING, data, false);
118+
assert!(data.len() % 8 == 0 || result.is_err());
119+
assert_eq!(
120+
result.err().unwrap(),
121+
stm32g4xx_hal::flash::Error::ArrayMustBeDivisibleBy8
122+
);
123+
124+
// This test should pass, as the data needs to be divisible by 8 and force padding is true.
125+
// For example, the one_byte array will be padded with 7 bytes of 0xFF
126+
let result =
127+
flash_writer.write(FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING, data, true);
128+
assert!(result.is_ok());
129+
logger::info!(
130+
"Wrote {} byte to address {}",
131+
data.len(),
132+
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING
133+
);
231134
}
232135

233-
logger::info!("Validating data written data by performing read and compare");
234-
235-
for i in 0..6 {
236-
match i {
237-
0 => {
238-
let bytes = flash_writer
239-
.read(FLASH_EXAMPLE_START_ADDRESS as u32, one_byte.len())
240-
.unwrap();
241-
assert!(compare_arrays(&bytes, &one_byte));
242-
logger::info!("Validated 1 byte data");
243-
}
244-
1 => {
245-
let bytes = flash_writer
246-
.read(
247-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
248-
two_bytes.len(),
249-
)
250-
.unwrap();
251-
assert!(compare_arrays(&bytes, &two_bytes));
252-
logger::info!("Validated 2 byte data");
253-
}
254-
2 => {
255-
let bytes = flash_writer
256-
.read(
257-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
258-
three_bytes.len(),
259-
)
260-
.unwrap();
261-
assert!(compare_arrays(&bytes, &three_bytes));
262-
logger::info!("Validated 3 byte data");
263-
}
264-
3 => {
265-
let bytes = flash_writer
266-
.read(
267-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
268-
four_bytes.len(),
269-
)
270-
.unwrap();
271-
assert!(compare_arrays(&bytes, &four_bytes));
272-
logger::info!("Validated 4 byte data");
273-
}
274-
4 => {
275-
let bytes = flash_writer
276-
.read(
277-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
278-
eight_bytes.len(),
279-
)
280-
.unwrap();
281-
assert!(compare_arrays(&bytes, &eight_bytes));
282-
logger::info!("Validated 8 byte data");
283-
}
284-
5 => {
285-
let bytes = flash_writer
286-
.read(
287-
FLASH_EXAMPLE_START_ADDRESS + i * FLASH_SPACING,
288-
sixteen_bytes.len(),
289-
)
290-
.unwrap();
291-
assert!(compare_arrays(&bytes, &sixteen_bytes));
292-
logger::info!("Validated 5 byte data");
293-
}
294-
_ => (),
295-
}
136+
logger::info!("Validating data written by performing read and compare");
137+
138+
for (i, data) in data.iter().enumerate() {
139+
let bytes = flash_writer
140+
.read(
141+
FLASH_EXAMPLE_START_ADDRESS + i as u32 * FLASH_SPACING,
142+
data.len(),
143+
)
144+
.unwrap();
145+
assert_eq!(&bytes, data);
146+
logger::info!("Validated {} byte data", data.len());
296147
}
297148

298149
logger::info!(

‎src/can.rs

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,6 @@ mod sealed {
1111
pub trait Rx<CAN> {}
1212
}
1313

14-
/// Select an FDCAN Clock Source
15-
#[allow(clippy::upper_case_acronyms)]
16-
#[allow(dead_code)]
17-
enum FdCanClockSource {
18-
/// Select HSE as the FDCAN clock source
19-
HSE = 0b00,
20-
/// Select PLL "Q" clock as the FDCAN clock source
21-
PLLQ = 0b01,
22-
/// Select "P" clock as the FDCAN clock source
23-
PCLK = 0b10,
24-
//Reserved = 0b10,
25-
}
26-
2714
/// Storage type for the CAN controller
2815
#[derive(Debug)]
2916
pub struct Can<FDCAN> {
@@ -55,18 +42,6 @@ where
5542
{
5643
Self::enable(&rcc.rb);
5744

58-
if rcc.rb.ccipr().read().fdcansel().is_hse() {
59-
// Select P clock as FDCAN clock source
60-
rcc.rb.ccipr().modify(|_, w| {
61-
// This is sound, as `FdCanClockSource` only contains valid values for this field.
62-
unsafe {
63-
w.fdcansel().bits(FdCanClockSource::PCLK as u8);
64-
}
65-
66-
w
67-
});
68-
}
69-
7045
self.fdcan_unchecked()
7146
}
7247

‎src/flash.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ pub struct FlashWriter<'a, const SECTOR_SZ_KB: u32> {
5858
flash_sz: FlashSize,
5959
verify: bool,
6060
}
61-
impl<'a, const SECTOR_SZ_KB: u32> FlashWriter<'a, SECTOR_SZ_KB> {
61+
impl<const SECTOR_SZ_KB: u32> FlashWriter<'_, SECTOR_SZ_KB> {
6262
#[allow(unused)]
6363
fn unlock_options(&mut self) -> Result<()> {
6464
// Check if flash is busy

‎src/rcc/config.rs

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,18 @@ impl Default for PllConfig {
325325
}
326326
}
327327

328+
/// FDCAN Clock Source
329+
#[allow(clippy::upper_case_acronyms)]
330+
pub enum FdCanClockSource {
331+
/// Select HSE as the FDCAN clock source
332+
HSE = 0b00,
333+
/// Select PLL "Q" clock as the FDCAN clock source
334+
PLLQ = 0b01,
335+
/// Select "P" clock as the FDCAN clock source
336+
PCLK = 0b10,
337+
//Reserved = 0b10,
338+
}
339+
328340
/// Clocks configutation
329341
pub struct Config {
330342
pub(crate) sys_mux: SysClockSrc,
@@ -335,6 +347,8 @@ pub struct Config {
335347

336348
/// Required for f_sys > 150MHz
337349
pub(crate) enable_boost: bool,
350+
351+
pub(crate) fdcansel: FdCanClockSource,
338352
}
339353

340354
impl Config {
@@ -379,6 +393,11 @@ impl Config {
379393
self.enable_boost = enable_boost;
380394
self
381395
}
396+
397+
pub fn fdcan_src(mut self, mux: FdCanClockSource) -> Self {
398+
self.fdcansel = mux;
399+
self
400+
}
382401
}
383402

384403
impl Default for Config {
@@ -390,6 +409,7 @@ impl Default for Config {
390409
apb1_psc: Prescaler::NotDivided,
391410
apb2_psc: Prescaler::NotDivided,
392411
enable_boost: false,
412+
fdcansel: FdCanClockSource::HSE,
393413
}
394414
}
395415
}

‎src/rcc/mod.rs

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,12 @@ impl Rcc {
216216
_ => apb2_freq * 2,
217217
};
218218

219+
// Configure FDCAN clock source.
220+
self.rb.ccipr().modify(|_, w| unsafe {
221+
// This is sound, as `FdCanClockSource` only contains valid values for this field.
222+
w.fdcansel().bits(rcc_cfg.fdcansel as u8)
223+
});
224+
219225
Rcc {
220226
rb: self.rb,
221227
clocks: Clocks {
@@ -408,7 +414,7 @@ impl Rcc {
408414
let us_per_s = 1_000_000;
409415
// Number of cycles @ sys_freq for 1us, rounded up, this will
410416
// likely end up being 2us since the AHB prescaler is changed
411-
let delay_cycles = (sys_freq + us_per_s - 1) / us_per_s;
417+
let delay_cycles = sys_freq.div_ceil(us_per_s);
412418
cortex_m::asm::delay(delay_cycles);
413419

414420
self.rb

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