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techmccatusbalbin
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spi: nicer field setters for bidimode
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src/spi.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -198,13 +198,13 @@ impl<SPI: Instance, PINS> Spi<SPI, PINS> {
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pub fn set_tx_only(&mut self) {
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self.spi
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.cr1()
201-
.modify(|_, w| w.bidimode().set_bit().bidioe().set_bit());
201+
.modify(|_, w| w.bidimode().bidirectional().bidioe().output_enabled());
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}
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#[inline]
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pub fn set_bidi(&mut self) {
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self.spi
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.cr1()
207-
.modify(|_, w| w.bidimode().clear_bit().bidioe().clear_bit());
207+
.modify(|_, w| w.bidimode().unidirectional().bidioe().output_disabled());
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}
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fn tx_fifo_cap(&self) -> u8 {
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match self.spi.sr().read().ftlvl().bits() {
@@ -271,7 +271,7 @@ fn setup_spi_regs(regs: &spi1::RegisterBlock, spi_freq: u32, bus_freq: u32, mode
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.rxonly()
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.clear_bit()
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.bidimode()
274-
.clear_bit()
274+
.unidirectional()
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.ssi()
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.set_bit()
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.spe()

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