diff --git a/Cargo.toml b/Cargo.toml
index 84d4bc39..10308a46 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -13,8 +13,8 @@ version = "0.0.2"
 
 [dependencies]
 nb = "0.1.1"
-#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
-stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
+stm32g4 = { path = "../stm32-rs/stm32g4" } #git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
+#stm32g4 = { version = "0.19.0", package = "stm32g4-staging" }
 paste = "1.0"
 bitflags = "1.2"
 vcell = "0.1"
diff --git a/src/adc.rs b/src/adc.rs
index 600e8bcf..e46e1e0c 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -1663,14 +1663,14 @@ macro_rules! adc {
                     self.calibrate_all();
                     self.apply_config(self.config);
 
-                    self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
+                    self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
                     self.adc_reg.cr().modify(|_, w| w.aden().set_bit());
 
                     // Wait for adc to get ready
                     while !self.adc_reg.isr().read().adrdy().bit_is_set() {}
 
                     // Clear ready flag
-                    self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit());
+                    self.adc_reg.isr().modify(|_, w| w.adrdy().clear());
 
                     self.clear_end_of_conversion_flag();
                 }
@@ -1841,25 +1841,25 @@ macro_rules! adc {
                     self.config.difsel = df;
 
                     self.adc_reg.difsel().modify(|_, w| {w
-                        .difsel_0().bit(df.get_channel(0).into() )
-                        .difsel_1().bit(df.get_channel(1).into() )
-                        .difsel_2().bit(df.get_channel(2).into() )
-                        .difsel_3().bit(df.get_channel(3).into() )
-                        .difsel_4().bit(df.get_channel(4).into() )
-                        .difsel_5().bit(df.get_channel(5).into() )
-                        .difsel_6().bit(df.get_channel(6).into() )
-                        .difsel_7().bit(df.get_channel(7).into() )
-                        .difsel_8().bit(df.get_channel(8).into() )
-                        .difsel_9().bit(df.get_channel(9).into() )
-                        .difsel_10().bit(df.get_channel(10).into() )
-                        .difsel_11().bit(df.get_channel(11).into() )
-                        .difsel_12().bit(df.get_channel(12).into() )
-                        .difsel_13().bit(df.get_channel(13).into() )
-                        .difsel_14().bit(df.get_channel(14).into() )
-                        .difsel_15().bit(df.get_channel(15).into() )
-                        .difsel_16().bit(df.get_channel(16).into() )
-                        .difsel_17().bit(df.get_channel(17).into() )
-                        .difsel_18().bit(df.get_channel(18).into() )
+                        .difsel0().bit(df.get_channel(0).into() )
+                        .difsel1().bit(df.get_channel(1).into() )
+                        .difsel2().bit(df.get_channel(2).into() )
+                        .difsel3().bit(df.get_channel(3).into() )
+                        .difsel4().bit(df.get_channel(4).into() )
+                        .difsel5().bit(df.get_channel(5).into() )
+                        .difsel6().bit(df.get_channel(6).into() )
+                        .difsel7().bit(df.get_channel(7).into() )
+                        .difsel8().bit(df.get_channel(8).into() )
+                        .difsel9().bit(df.get_channel(9).into() )
+                        .difsel10().bit(df.get_channel(10).into() )
+                        .difsel11().bit(df.get_channel(11).into() )
+                        .difsel12().bit(df.get_channel(12).into() )
+                        .difsel13().bit(df.get_channel(13).into() )
+                        .difsel14().bit(df.get_channel(14).into() )
+                        .difsel15().bit(df.get_channel(15).into() )
+                        .difsel16().bit(df.get_channel(16).into() )
+                        .difsel17().bit(df.get_channel(17).into() )
+                        .difsel18().bit(df.get_channel(18).into() )
                     });
                 }
 
@@ -2015,7 +2015,7 @@ macro_rules! adc {
                 /// Resets the end-of-conversion flag
                 #[inline(always)]
                 pub fn clear_end_of_conversion_flag(&mut self) {
-                    self.adc_reg.isr().modify(|_, w| w.eoc().set_bit());
+                    self.adc_reg.isr().modify(|_, w| w.eoc().clear());
                 }
 
                 /// Block until the conversion is completed and return to configured
@@ -2124,7 +2124,7 @@ macro_rules! adc {
                 /// Resets the overrun flag
                 #[inline(always)]
                 pub fn clear_overrun_flag(&mut self) {
-                    self.adc_reg.isr().modify(|_, w| w.ovr().set_bit());
+                    self.adc_reg.isr().modify(|_, w| w.ovr().clear());
                 }
             }
 
diff --git a/src/dma/channel.rs b/src/dma/channel.rs
index 58f30814..66f188b0 100644
--- a/src/dma/channel.rs
+++ b/src/dma/channel.rs
@@ -91,9 +91,9 @@ pub trait DMAExt<I> {
 impl DMAExt<Self> for DMA1 {
     fn split(self, rcc: &Rcc) -> Channels<DMA1> {
         // Enable DMAMux is not yet enabled
-        if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
+        if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
             // Enable peripheral
-            rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
+            rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
         }
 
         // Enable peripheral
@@ -106,9 +106,9 @@ impl DMAExt<Self> for DMA1 {
 impl DMAExt<Self> for DMA2 {
     fn split(self, rcc: &Rcc) -> Channels<DMA2> {
         // Enable DMAMux is not yet enabled
-        if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() {
+        if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() {
             // Enable peripheral
-            rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit());
+            rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit());
         }
 
         // Enable peripheral
diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs
index 9030093e..e9e3e1ad 100644
--- a/src/rcc/mod.rs
+++ b/src/rcc/mod.rs
@@ -455,7 +455,7 @@ impl Rcc {
         let csr = self.rb.csr().read();
 
         ResetReason {
-            low_power: csr.lpwrstf().bit(),
+            low_power: csr.lpwrrstf().bit(),
             window_watchdog: csr.wwdgrstf().bit(),
             independent_watchdog: csr.iwdgrstf().bit(),
             software: csr.sftrstf().bit(),