From 0c3dff03c182863bb137a6d8890b305f572b848f Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Sun, 22 Dec 2024 22:42:36 +0100 Subject: [PATCH 1/2] Update for new pac stm32-rs/stm32-rs#1074 --- Cargo.toml | 4 ++-- src/adc.rs | 46 +++++++++++++++++++++++----------------------- src/dma/channel.rs | 8 ++++---- src/pwr.rs | 10 +++++----- src/rcc/mod.rs | 4 ++-- 5 files changed, 36 insertions(+), 36 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 84d4bc39..10308a46 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,8 +13,8 @@ version = "0.0.2" [dependencies] nb = "0.1.1" -#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1" -stm32g4 = { version = "0.19.0", package = "stm32g4-staging" } +stm32g4 = { path = "../stm32-rs/stm32g4" } #git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1" +#stm32g4 = { version = "0.19.0", package = "stm32g4-staging" } paste = "1.0" bitflags = "1.2" vcell = "0.1" diff --git a/src/adc.rs b/src/adc.rs index 600e8bcf..e46e1e0c 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1663,14 +1663,14 @@ macro_rules! adc { self.calibrate_all(); self.apply_config(self.config); - self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit()); + self.adc_reg.isr().modify(|_, w| w.adrdy().clear()); self.adc_reg.cr().modify(|_, w| w.aden().set_bit()); // Wait for adc to get ready while !self.adc_reg.isr().read().adrdy().bit_is_set() {} // Clear ready flag - self.adc_reg.isr().modify(|_, w| w.adrdy().set_bit()); + self.adc_reg.isr().modify(|_, w| w.adrdy().clear()); self.clear_end_of_conversion_flag(); } @@ -1841,25 +1841,25 @@ macro_rules! adc { self.config.difsel = df; self.adc_reg.difsel().modify(|_, w| {w - .difsel_0().bit(df.get_channel(0).into() ) - .difsel_1().bit(df.get_channel(1).into() ) - .difsel_2().bit(df.get_channel(2).into() ) - .difsel_3().bit(df.get_channel(3).into() ) - .difsel_4().bit(df.get_channel(4).into() ) - .difsel_5().bit(df.get_channel(5).into() ) - .difsel_6().bit(df.get_channel(6).into() ) - .difsel_7().bit(df.get_channel(7).into() ) - .difsel_8().bit(df.get_channel(8).into() ) - .difsel_9().bit(df.get_channel(9).into() ) - .difsel_10().bit(df.get_channel(10).into() ) - .difsel_11().bit(df.get_channel(11).into() ) - .difsel_12().bit(df.get_channel(12).into() ) - .difsel_13().bit(df.get_channel(13).into() ) - .difsel_14().bit(df.get_channel(14).into() ) - .difsel_15().bit(df.get_channel(15).into() ) - .difsel_16().bit(df.get_channel(16).into() ) - .difsel_17().bit(df.get_channel(17).into() ) - .difsel_18().bit(df.get_channel(18).into() ) + .difsel0().bit(df.get_channel(0).into() ) + .difsel1().bit(df.get_channel(1).into() ) + .difsel2().bit(df.get_channel(2).into() ) + .difsel3().bit(df.get_channel(3).into() ) + .difsel4().bit(df.get_channel(4).into() ) + .difsel5().bit(df.get_channel(5).into() ) + .difsel6().bit(df.get_channel(6).into() ) + .difsel7().bit(df.get_channel(7).into() ) + .difsel8().bit(df.get_channel(8).into() ) + .difsel9().bit(df.get_channel(9).into() ) + .difsel10().bit(df.get_channel(10).into() ) + .difsel11().bit(df.get_channel(11).into() ) + .difsel12().bit(df.get_channel(12).into() ) + .difsel13().bit(df.get_channel(13).into() ) + .difsel14().bit(df.get_channel(14).into() ) + .difsel15().bit(df.get_channel(15).into() ) + .difsel16().bit(df.get_channel(16).into() ) + .difsel17().bit(df.get_channel(17).into() ) + .difsel18().bit(df.get_channel(18).into() ) }); } @@ -2015,7 +2015,7 @@ macro_rules! adc { /// Resets the end-of-conversion flag #[inline(always)] pub fn clear_end_of_conversion_flag(&mut self) { - self.adc_reg.isr().modify(|_, w| w.eoc().set_bit()); + self.adc_reg.isr().modify(|_, w| w.eoc().clear()); } /// Block until the conversion is completed and return to configured @@ -2124,7 +2124,7 @@ macro_rules! adc { /// Resets the overrun flag #[inline(always)] pub fn clear_overrun_flag(&mut self) { - self.adc_reg.isr().modify(|_, w| w.ovr().set_bit()); + self.adc_reg.isr().modify(|_, w| w.ovr().clear()); } } diff --git a/src/dma/channel.rs b/src/dma/channel.rs index 58f30814..66f188b0 100644 --- a/src/dma/channel.rs +++ b/src/dma/channel.rs @@ -91,9 +91,9 @@ pub trait DMAExt { impl DMAExt for DMA1 { fn split(self, rcc: &Rcc) -> Channels { // Enable DMAMux is not yet enabled - if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() { + if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() { // Enable peripheral - rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit()); + rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit()); } // Enable peripheral @@ -106,9 +106,9 @@ impl DMAExt for DMA1 { impl DMAExt for DMA2 { fn split(self, rcc: &Rcc) -> Channels { // Enable DMAMux is not yet enabled - if !rcc.rb.ahb1enr().read().dmamuxen().bit_is_set() { + if !rcc.rb.ahb1enr().read().dmamux1en().bit_is_set() { // Enable peripheral - rcc.rb.ahb1enr().modify(|_, w| w.dmamuxen().set_bit()); + rcc.rb.ahb1enr().modify(|_, w| w.dmamux1en().set_bit()); } // Enable peripheral diff --git a/src/pwr.rs b/src/pwr.rs index f451fbc7..e7623064 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -103,10 +103,10 @@ pub(crate) fn current_vos() -> VoltageScale { // NOTE(unsafe): Read-only access let pwr = unsafe { &*PWR::ptr() }; - match pwr.cr1().read().vos().bits() { + match pwr.pwr_cr1().read().vos().bits() { 0b00 => unreachable!(), 0b01 => VoltageScale::Range1 { - enable_boost: pwr.cr5().read().r1mode().bit(), + enable_boost: pwr.pwr_cr5().read().r1mode().bit(), }, 0b10 => VoltageScale::Range2, 0b11 => unreachable!(), @@ -129,10 +129,10 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) { VoltageScale::Range1 { .. } => 0b01, VoltageScale::Range2 => 0b10, }; - pwr.cr1().modify(|_r, w| w.vos().bits(vos)); + pwr.pwr_cr1().modify(|_r, w| w.vos().bits(vos)); // Wait for ready - while pwr.sr2().read().vosf().bit() {} + while pwr.pwr_sr2().read().vosf().bit() {} } /// Set new voltage scale @@ -143,5 +143,5 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) { pub(crate) unsafe fn set_boost(enable_boost: bool) { let pwr = unsafe { &*PWR::ptr() }; let r1mode = !enable_boost; - pwr.cr5().modify(|_r, w| w.r1mode().bit(r1mode)); + pwr.pwr_cr5().modify(|_r, w| w.r1mode().bit(r1mode)); } diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 9030093e..021aacff 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -240,7 +240,7 @@ impl Rcc { pub fn unlock_rtc(&mut self) { self.rb.apb1enr1().modify(|_, w| w.pwren().set_bit()); let pwr = unsafe { &(*PWR::ptr()) }; - pwr.cr1().modify(|_, w| w.dbp().set_bit()); + pwr.pwr_cr1().modify(|_, w| w.dbp().set_bit()); } fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks { @@ -455,7 +455,7 @@ impl Rcc { let csr = self.rb.csr().read(); ResetReason { - low_power: csr.lpwrstf().bit(), + low_power: csr.lpwrrstf().bit(), window_watchdog: csr.wwdgrstf().bit(), independent_watchdog: csr.iwdgrstf().bit(), software: csr.sftrstf().bit(), From a950cc2c441c1e249ae5338a1d9e49538b983329 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Sun, 22 Dec 2024 23:13:00 +0100 Subject: [PATCH 2/2] Update for removed pwr_ prefix --- src/pwr.rs | 10 +++++----- src/rcc/mod.rs | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/pwr.rs b/src/pwr.rs index e7623064..f451fbc7 100644 --- a/src/pwr.rs +++ b/src/pwr.rs @@ -103,10 +103,10 @@ pub(crate) fn current_vos() -> VoltageScale { // NOTE(unsafe): Read-only access let pwr = unsafe { &*PWR::ptr() }; - match pwr.pwr_cr1().read().vos().bits() { + match pwr.cr1().read().vos().bits() { 0b00 => unreachable!(), 0b01 => VoltageScale::Range1 { - enable_boost: pwr.pwr_cr5().read().r1mode().bit(), + enable_boost: pwr.cr5().read().r1mode().bit(), }, 0b10 => VoltageScale::Range2, 0b11 => unreachable!(), @@ -129,10 +129,10 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) { VoltageScale::Range1 { .. } => 0b01, VoltageScale::Range2 => 0b10, }; - pwr.pwr_cr1().modify(|_r, w| w.vos().bits(vos)); + pwr.cr1().modify(|_r, w| w.vos().bits(vos)); // Wait for ready - while pwr.pwr_sr2().read().vosf().bit() {} + while pwr.sr2().read().vosf().bit() {} } /// Set new voltage scale @@ -143,5 +143,5 @@ pub(crate) unsafe fn set_vos(vos: VoltageScale) { pub(crate) unsafe fn set_boost(enable_boost: bool) { let pwr = unsafe { &*PWR::ptr() }; let r1mode = !enable_boost; - pwr.pwr_cr5().modify(|_r, w| w.r1mode().bit(r1mode)); + pwr.cr5().modify(|_r, w| w.r1mode().bit(r1mode)); } diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 021aacff..e9e3e1ad 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -240,7 +240,7 @@ impl Rcc { pub fn unlock_rtc(&mut self) { self.rb.apb1enr1().modify(|_, w| w.pwren().set_bit()); let pwr = unsafe { &(*PWR::ptr()) }; - pwr.pwr_cr1().modify(|_, w| w.dbp().set_bit()); + pwr.cr1().modify(|_, w| w.dbp().set_bit()); } fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks {