diff --git a/examples/can-echo.rs b/examples/can-echo.rs index 5301ad8a..2f8c0890 100644 --- a/examples/can-echo.rs +++ b/examples/can-echo.rs @@ -6,7 +6,7 @@ use crate::hal::{ gpio::{GpioExt as _, Speed}, nb::block, pwr::PwrExt, - rcc::{Config, RccExt, SysClockSrc}, + rcc::{Config, RccExt}, stm32::Peripherals, time::RateExtU32, }; @@ -49,7 +49,7 @@ fn main() -> ! { let pwr = dp.PWR.constrain().freeze(); let rcc = dp.RCC.constrain(); - let mut rcc = rcc.freeze(Config::new(SysClockSrc::HSE(24.MHz())), pwr); + let mut rcc = rcc.freeze(Config::hse(24.MHz()), pwr); info!("Split GPIO"); @@ -61,7 +61,7 @@ fn main() -> ! { let tx = gpiob.pb9.into_alternate().speed(Speed::VeryHigh); info!("-- Create CAN 1 instance"); - let mut can = dp.FDCAN1.fdcan(tx, rx, &rcc); + let mut can = dp.FDCAN1.fdcan(tx, rx, &mut rcc); can.set_protocol_exception_handling(false); info!("-- Configure nominal timing"); diff --git a/examples/i2c-mpu6050.rs b/examples/i2c-mpu6050.rs index a9bf69ad..7086e8da 100644 --- a/examples/i2c-mpu6050.rs +++ b/examples/i2c-mpu6050.rs @@ -3,7 +3,6 @@ #![no_main] #![no_std] -use hal::i2c::Config; use hal::prelude::*; use hal::stm32; use hal::time::{ExtU32, RateExtU32}; @@ -29,7 +28,7 @@ fn main() -> ! { let sda = gpiob.pb9.into_alternate_open_drain(); let scl = gpiob.pb8.into_alternate_open_drain(); - let i2c = dp.I2C1.i2c(sda, scl, Config::new(100.kHz()), &mut rcc); + let i2c = dp.I2C1.i2c(sda, scl, 100.kHz(), &mut rcc); let mut mpu = Mpu6050::new(i2c); let mut delay = cp.SYST.delay(&rcc.clocks); diff --git a/examples/i2c.rs b/examples/i2c.rs index beea9ae2..4bf0366e 100644 --- a/examples/i2c.rs +++ b/examples/i2c.rs @@ -3,7 +3,6 @@ #![no_main] #![no_std] -use hal::i2c::Config; use hal::prelude::*; use hal::stm32; use hal::time::RateExtU32; @@ -26,7 +25,7 @@ fn main() -> ! { let sda = gpiob.pb9.into_alternate_open_drain(); let scl = gpiob.pb8.into_alternate_open_drain(); - let mut i2c = dp.I2C1.i2c(sda, scl, Config::new(40.kHz()), &mut rcc); + let mut i2c = dp.I2C1.i2c(sda, scl, 40.kHz(), &mut rcc); // Alternatively, it is possible to specify the exact timing as follows (see the documentation // of with_timing() for an explanation of the constant): //let mut i2c = dp diff --git a/src/adc/mod.rs b/src/adc/mod.rs index e1442216..9ed3a903 100644 --- a/src/adc/mod.rs +++ b/src/adc/mod.rs @@ -49,11 +49,8 @@ fn init_adc_common( ) -> AdcCommon { let cfg = cfg.to_bits(rcc); - unsafe { - let rcc_ptr = &(*stm32::RCC::ptr()); - ADCC::enable(rcc_ptr); - ADCC::reset(rcc_ptr); - } + ADCC::enable(rcc); + ADCC::reset(rcc); // Select system clock as ADC clock source rcc.rb diff --git a/src/can.rs b/src/can.rs index 0dda3c68..8e89eb14 100644 --- a/src/can.rs +++ b/src/can.rs @@ -33,13 +33,13 @@ where self, _tx: TX, _rx: RX, - rcc: &Rcc, + rcc: &mut Rcc, ) -> fdcan::FdCan, fdcan::ConfigMode> where TX: sealed::Tx, RX: sealed::Rx, { - Self::enable(&rcc.rb); + Self::enable(rcc); self.fdcan_unchecked() } diff --git a/src/dac.rs b/src/dac.rs index d253b24d..874bf688 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -13,7 +13,6 @@ use crate::gpio::{Analog, PA4, PA5, PA6}; use crate::pac; use crate::rcc::{self, *}; use crate::stm32::dac1::mcr::HFSEL; -use crate::stm32::RCC; use embedded_hal::delay::DelayNs; pub trait DacOut { @@ -458,15 +457,12 @@ pub trait DacExt: Sized { } impl DacExt for DAC { - fn constrain(self, _pins: PINS, _rcc: &mut Rcc) -> PINS::Output + fn constrain(self, _pins: PINS, rcc: &mut Rcc) -> PINS::Output where PINS: Pins, { - unsafe { - let rcc_ptr = &(*RCC::ptr()); - Self::enable(rcc_ptr); - Self::reset(rcc_ptr); - } + Self::enable(rcc); + Self::reset(rcc); #[allow(clippy::uninit_assumed_init)] unsafe { diff --git a/src/delay.rs b/src/delay.rs index 1b869adf..3e0b3faa 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -119,17 +119,12 @@ impl DelayMs for SystDelay { } pub trait DelayExt { - fn delay(&mut self, delay: T) - where - T: Into; + fn delay(&mut self, delay: MicroSecond); } impl DelayExt for SystDelay { - fn delay(&mut self, delay: T) - where - T: Into, - { - self.0.delay_us(delay.into().ticks()) + fn delay(&mut self, delay: MicroSecond) { + self.0.delay_us(delay.ticks()) } } diff --git a/src/gpio.rs b/src/gpio.rs index 7fd05d5f..7923142d 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -582,8 +582,8 @@ macro_rules! gpio { type Parts = Parts; fn split(self, rcc: &mut Rcc) -> Parts { - Self::enable(&rcc.rb); - Self::reset(&rcc.rb); + Self::enable(rcc); + Self::reset(rcc); Parts { $( diff --git a/src/i2c.rs b/src/i2c.rs index 9129679d..272af5bb 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -12,7 +12,7 @@ use crate::rcc::{Enable, GetBusFreq, Rcc, RccBus, Reset}; feature = "stm32g484" ))] use crate::stm32::I2C4; -use crate::stm32::{I2C1, I2C2, I2C3, RCC}; +use crate::stm32::{I2C1, I2C2, I2C3}; use crate::time::Hertz; use core::cmp; use core::convert::TryInto; @@ -29,12 +29,9 @@ pub struct Config { impl Config { /// Creates a default configuration for the given bus frequency. - pub fn new(speed: T) -> Self - where - T: Into, - { + pub fn new(speed: Hertz) -> Self { Config { - speed: Some(speed.into()), + speed: Some(speed), timing: None, analog_filter: true, digital_filter: 0, @@ -98,16 +95,17 @@ impl Config { (psc, scll, sclh, sdadel, scldel) }; - reg.presc() - .set(psc.try_into().unwrap()) - .scldel() - .set(scldel) - .sdadel() - .set(sdadel) - .sclh() - .set(sclh.try_into().unwrap()) - .scll() - .set(scll.try_into().unwrap()) + reg.presc().set(psc.try_into().unwrap()); + reg.scldel().set(scldel); + reg.sdadel().set(sdadel); + reg.sclh().set(sclh.try_into().unwrap()); + reg.scll().set(scll.try_into().unwrap()) + } +} + +impl From for Config { + fn from(value: Hertz) -> Self { + Self::new(value) } } @@ -149,7 +147,13 @@ impl embedded_hal::i2c::Error for Error { } pub trait I2cExt { - fn i2c(self, sda: SDA, scl: SCL, config: Config, rcc: &mut Rcc) -> I2c + fn i2c( + self, + sda: SDA, + scl: SCL, + config: impl Into, + rcc: &mut Rcc, + ) -> I2c where SDA: SDAPin, SCL: SCLPin; @@ -216,7 +220,7 @@ macro_rules! i2c { self, sda: SDA, scl: SCL, - config: Config, + config: impl Into, rcc: &mut Rcc, ) -> I2c<$I2CX, SDA, SCL> where @@ -232,17 +236,15 @@ macro_rules! i2c { SCL: SCLPin<$I2CX> { /// Initializes the I2C peripheral. - pub fn $i2cx(i2c: $I2CX, sda: SDA, scl: SCL, config: Config, rcc: &mut Rcc) -> Self + pub fn $i2cx(i2c: $I2CX, sda: SDA, scl: SCL, config: impl Into, rcc: &mut Rcc) -> Self where SDA: SDAPin<$I2CX>, SCL: SCLPin<$I2CX>, { + let config = config.into(); // Enable and reset I2C - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $I2CX::enable(rcc_ptr); - $I2CX::reset(rcc_ptr); - } + $I2CX::enable(rcc); + $I2CX::reset(rcc); // Make sure the I2C unit is disabled so we can configure it i2c.cr1().modify(|_, w| w.pe().clear_bit()); @@ -252,12 +254,9 @@ macro_rules! i2c { // Enable the I2C processing i2c.cr1().modify(|_, w| { - w.pe() - .set_bit() - .dnf() - .set(config.digital_filter) - .anfoff() - .bit(!config.analog_filter) + w.pe().set_bit(); + w.dnf().set(config.digital_filter); + w.anfoff().bit(!config.analog_filter) }); I2c { i2c, sda, scl } @@ -267,9 +266,8 @@ macro_rules! i2c { pub fn release(self) -> ($I2CX, SDA, SCL) { // Disable I2C. unsafe { - let rcc_ptr = &(*RCC::ptr()); - $I2CX::reset(rcc_ptr); - $I2CX::disable(rcc_ptr); + $I2CX::reset_unchecked(); + $I2CX::disable_unchecked(); } (self.i2c, self.sda, self.scl) diff --git a/src/pwm.rs b/src/pwm.rs index a69c2746..fe92f9ec 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -173,7 +173,6 @@ use core::marker::PhantomData; use core::mem::MaybeUninit; use crate::stm32::LPTIMER1; -use crate::stm32::RCC; #[cfg(any( feature = "stm32g473", feature = "stm32g474", @@ -1147,11 +1146,8 @@ macro_rules! tim_hal { where PINS: Pins<$TIMX, T, U>, { - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $TIMX::enable(rcc_ptr); - $TIMX::reset(rcc_ptr); - } + $TIMX::enable(rcc); + $TIMX::reset(rcc); let clk = $TIMX::get_timer_frequency(&rcc.clocks); @@ -1189,11 +1185,8 @@ macro_rules! tim_hal { where PINS: Pins { - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $TIMX::enable(rcc_ptr); - $TIMX::reset(rcc_ptr); - } + $TIMX::enable(rcc); + $TIMX::reset(rcc); let clk = $TIMX::get_timer_frequency(&rcc.clocks).raw(); @@ -1801,11 +1794,8 @@ macro_rules! lptim_hal { where PINS: Pins<$TIMX, T, U>, { - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $TIMX::enable(rcc_ptr); - $TIMX::reset(rcc_ptr); - } + $TIMX::enable(rcc); + $TIMX::reset(rcc); let clk = $TIMX::get_timer_frequency(&rcc.clocks); let reload = clk / freq; diff --git a/src/rcc/clockout.rs b/src/rcc/clockout.rs index 3cd85cf1..5858af99 100644 --- a/src/rcc/clockout.rs +++ b/src/rcc/clockout.rs @@ -1,6 +1,6 @@ use crate::gpio::*; +use crate::pac::RCC; use crate::rcc::*; -use crate::stm32::RCC; pub type LscoPin = gpioa::PA2; diff --git a/src/rcc/config.rs b/src/rcc/config.rs index 79eb7124..1e95f450 100644 --- a/src/rcc/config.rs +++ b/src/rcc/config.rs @@ -392,6 +392,10 @@ impl Config { Config::const_default().clock_src(SysClockSrc::HSI) } + pub const fn hse(freq: Hertz) -> Self { + Config::const_default().clock_src(SysClockSrc::HSE(freq)) + } + pub const fn clock_src(mut self, mux: SysClockSrc) -> Self { self.sys_mux = mux; self diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs index 1d3523eb..bef92b05 100644 --- a/src/rcc/enable.rs +++ b/src/rcc/enable.rs @@ -5,7 +5,7 @@ macro_rules! bus_enable { ($PER:ident => ($busX:ty, $bit:literal)) => { impl Enable for crate::stm32::$PER { #[inline(always)] - fn enable(rcc: &RccRB) { + fn enable(rcc: &mut RCC) { unsafe { bb::set(Self::Bus::enr(rcc), $bit); } @@ -13,17 +13,41 @@ macro_rules! bus_enable { // cortex_m::asm::dsb(); } #[inline(always)] - fn disable(rcc: &RccRB) { + fn disable(rcc: &mut RCC) { unsafe { bb::clear(Self::Bus::enr(rcc), $bit); } } + #[inline(always)] + fn is_enabled() -> bool { + let rcc = unsafe { &*RCC::ptr() }; + (Self::Bus::enr(rcc).read().bits() >> $bit) & 0x1 != 0 + } + } + }; +} +macro_rules! bus_smenable { + ($PER:ident => ($busX:ty, $bit:literal)) => { + impl SMEnable for crate::stm32::$PER { #[inline(always)] - fn enable_for_sleep_stop(rcc: &RccRB) { + fn sleep_mode_enable(rcc: &mut RCC) { unsafe { bb::set(Self::Bus::smenr(rcc), $bit); } + // // Stall the pipeline to work around erratum 2.1.13 (DM00037591) + // cortex_m::asm::dsb(); + } + #[inline(always)] + fn sleep_mode_disable(rcc: &mut RCC) { + unsafe { + bb::clear(Self::Bus::smenr(rcc), $bit); + } + } + #[inline(always)] + fn is_sleep_mode_enabled() -> bool { + let rcc = unsafe { &*RCC::ptr() }; + (Self::Bus::smenr(rcc).read().bits() >> $bit) & 0x1 != 0 } } }; @@ -33,7 +57,7 @@ macro_rules! bus_reset { ($PER:ident => ($busX:ty, $bit:literal)) => { impl Reset for crate::stm32::$PER { #[inline(always)] - fn reset(rcc: &RccRB) { + fn reset(rcc: &mut RCC) { unsafe { bb::set(Self::Bus::rstr(rcc), $bit); bb::clear(Self::Bus::rstr(rcc), $bit); @@ -51,6 +75,7 @@ macro_rules! bus { } impl crate::rcc::Instance for crate::stm32::$PER {} bus_enable!($PER => ($busX, $bit)); + bus_smenable!($PER => ($busX, $bit)); bus_reset!($PER => ($busX, $bit)); )+ } diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index 544adc51..c5136b77 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -1,6 +1,7 @@ +use crate::pac::{rcc, FLASH, PWR, RCC}; use crate::pwr::{self, PowerConfiguration}; -use crate::stm32::{rcc, FLASH, PWR, RCC}; use crate::time::{Hertz, RateExtU32}; +use core::ops::{Deref, DerefMut}; mod clockout; mod config; @@ -75,6 +76,19 @@ pub struct Rcc { pub(crate) rb: RCC, } +impl Deref for Rcc { + type Target = RCC; + fn deref(&self) -> &Self::Target { + &self.rb + } +} + +impl DerefMut for Rcc { + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.rb + } +} + impl Rcc { /// Apply clock configuration pub fn freeze(mut self, rcc_cfg: Config, pwr_cfg: PowerConfiguration) -> Self { @@ -533,138 +547,129 @@ impl RccExt for RCC { use crate::stm32::rcc::RegisterBlock as RccRB; -pub struct AHB1 { - _0: (), -} -impl AHB1 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::AHB1ENR { - rcc.ahb1enr() - } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::AHB1RSTR { - rcc.ahb1rstr() - } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::AHB1SMENR { - rcc.ahb1smenr() - } -} +macro_rules! bus_struct { + ($($busX:ident => ($EN:ident, $en:ident, $SMEN:ident, $smenr:ident, $RST:ident, $rst:ident, $doc:literal),)+) => { + $( + #[doc = $doc] + #[non_exhaustive] + pub struct $busX; + + impl $busX { + #[allow(unused)] + pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN { + rcc.$en() + } -pub struct AHB2 { - _0: (), -} -impl AHB2 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::AHB2ENR { - rcc.ahb2enr() - } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::AHB2RSTR { - rcc.ahb2rstr() - } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::AHB2SMENR { - rcc.ahb2smenr() - } -} + #[allow(unused)] + pub(crate) fn smenr(rcc: &RccRB) -> &rcc::$SMEN { + rcc.$smenr() + } -pub struct AHB3 { - _0: (), + #[allow(unused)] + pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST { + rcc.$rst() + } + } + )+ + }; } -impl AHB3 { - #[allow(unused)] - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::AHB3ENR { - rcc.ahb3enr() - } - #[allow(unused)] - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::AHB3RSTR { - rcc.ahb3rstr() - } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::AHB3SMENR { - rcc.ahb3smenr() - } +use bus_struct; + +bus_struct! { + AHB1 => (AHB1ENR, ahb1enr, AHB1SMENR, ahb1smenr, AHB1RSTR, ahb1rstr, "Advanced High-performance Bus 1 (AHB1) registers"), + AHB2 => (AHB2ENR, ahb2enr, AHB2SMENR, ahb2smenr, AHB2RSTR, ahb2rstr, "Advanced High-performance Bus 2 (AHB2) registers"), + AHB3 => (AHB3ENR, ahb3enr, AHB3SMENR, ahb3smenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"), + APB1_1 => (APB1ENR1, apb1enr1, APB1SMENR1, apb1smenr1, APB1RSTR1, apb1rstr1, "Advanced Peripheral Bus 1 (APB1) block 1 registers"), + APB1_2 => (APB1ENR2, apb1enr2, APB1SMENR2, apb1smenr2, APB1RSTR2, apb1rstr2, "Advanced Peripheral Bus 1 (APB1) block 2 registers"), + APB2 => (APB2ENR, apb2enr, APB2SMENR, apb2smenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"), } -pub struct APB1_1 { - _0: (), -} -impl APB1_1 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::APB1ENR1 { - rcc.apb1enr1() - } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::APB1RSTR1 { - rcc.apb1rstr1() - } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::APB1SMENR1 { - rcc.apb1smenr1() - } +/// Bus associated to peripheral +pub trait RccBus: crate::Sealed { + /// Bus type; + type Bus; } -pub struct APB1_2 { - _0: (), -} -impl APB1_2 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::APB1ENR2 { - rcc.apb1enr2() +/// Enable/disable peripheral +pub trait Enable: RccBus { + /// Enables peripheral + fn enable(rcc: &mut RCC); + + /// Disables peripheral + fn disable(rcc: &mut RCC); + + /// Check if peripheral enabled + fn is_enabled() -> bool; + + /// Check if peripheral disabled + #[inline] + fn is_disabled() -> bool { + !Self::is_enabled() } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::APB1RSTR2 { - rcc.apb1rstr2() + + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn enable_unchecked() { + let mut rcc = RCC::steal(); + Self::enable(&mut rcc); } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::APB1SMENR2 { - rcc.apb1smenr2() + + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn disable_unchecked() { + let mut rcc = RCC::steal(); + Self::disable(&mut rcc); } } -pub struct APB2 { - _0: (), -} -impl APB2 { - #[inline(always)] - fn enr(rcc: &RccRB) -> &rcc::APB2ENR { - rcc.apb2enr() - } - #[inline(always)] - fn rstr(rcc: &RccRB) -> &rcc::APB2RSTR { - rcc.apb2rstr() - } - #[allow(unused)] - #[inline(always)] - fn smenr(rcc: &RccRB) -> &rcc::APB2SMENR { - rcc.apb2smenr() +/// Enable/disable peripheral in Sleep mode +pub trait SMEnable: RccBus { + /// Enables peripheral + fn sleep_mode_enable(rcc: &mut RCC); + + /// Disables peripheral + fn sleep_mode_disable(rcc: &mut RCC); + + /// Check if peripheral enabled + fn is_sleep_mode_enabled() -> bool; + + /// Check if peripheral disabled + #[inline] + fn is_sleep_mode_disabled() -> bool { + !Self::is_sleep_mode_enabled() } -} -/// Bus associated to peripheral -pub trait RccBus: crate::Sealed { - /// Bus type; - type Bus; -} + /// # Safety + /// + /// Enables peripheral. Takes access to RCC internally + unsafe fn sleep_mode_enable_unchecked() { + let mut rcc = RCC::steal(); + Self::sleep_mode_enable(&mut rcc); + } -/// Enable/disable peripheral -pub trait Enable: RccBus { - fn enable(rcc: &RccRB); - fn disable(rcc: &RccRB); - fn enable_for_sleep_stop(rcc: &RccRB); + /// # Safety + /// + /// Disables peripheral. Takes access to RCC internally + unsafe fn sleep_mode_disable_unchecked() { + let mut rcc = RCC::steal(); + Self::sleep_mode_disable(&mut rcc); + } } /// Reset peripheral pub trait Reset: RccBus { - fn reset(rcc: &RccRB); + /// Resets peripheral + fn reset(rcc: &mut RCC); + + /// # Safety + /// + /// Resets peripheral. Takes access to RCC internally + unsafe fn reset_unchecked() { + let mut rcc = RCC::steal(); + Self::reset(&mut rcc); + } } pub trait GetBusFreq { diff --git a/src/serial/usart.rs b/src/serial/usart.rs index 66ab45a6..e31755ff 100644 --- a/src/serial/usart.rs +++ b/src/serial/usart.rs @@ -490,8 +490,7 @@ macro_rules! uart_shared { // Disable the UART as well as its clock. self.tx.usart.cr1().modify(|_, w| w.ue().clear_bit()); unsafe { - let rcc_ptr = &(*RCC::ptr()); - $USARTX::disable(rcc_ptr); + $USARTX::disable_unchecked(); } (self.tx.usart, self.tx.pin, self.rx.pin) } @@ -556,11 +555,8 @@ macro_rules! uart_lp { rcc: &mut Rcc, ) -> Result { // Enable clock for USART - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $USARTX::enable(rcc_ptr); - $USARTX::reset(rcc_ptr); - } + $USARTX::enable(rcc); + $USARTX::reset(rcc); // TODO: By default, all UARTs are clocked from PCLK. We could modify RCC_CCIPR to // try SYSCLK if PCLK is not high enough. We could also select 8x oversampling @@ -703,11 +699,8 @@ macro_rules! uart_full { rcc: &mut Rcc, ) -> Result { // Enable clock for USART - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $USARTX::enable(rcc_ptr); - $USARTX::reset(rcc_ptr); - } + $USARTX::enable(rcc); + $USARTX::reset(rcc); // TODO: By default, all UARTs are clocked from PCLK. We could modify RCC_CCIPR to // try SYSCLK if PCLK is not high enough. We could also select 8x oversampling diff --git a/src/spi.rs b/src/spi.rs index 34e98847..9dd0e5c3 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -10,7 +10,7 @@ use crate::rcc::{Enable, GetBusFreq, Rcc, RccBus, Reset}; feature = "stm32g484" ))] use crate::stm32::SPI4; -use crate::stm32::{RCC, SPI1, SPI2, SPI3}; +use crate::stm32::{SPI1, SPI2, SPI3}; use crate::time::Hertz; use core::ptr; @@ -123,11 +123,8 @@ macro_rules! spi { T: Into { // Enable and reset SPI - unsafe { - let rcc_ptr = &(*RCC::ptr()); - $SPIX::enable(rcc_ptr); - $SPIX::reset(rcc_ptr); - } + $SPIX::enable(rcc); + $SPIX::reset(rcc); // disable SS output spi.cr2().write(|w| w.ssoe().disabled()); diff --git a/src/timer.rs b/src/timer.rs index c2a071a5..31eb7fd4 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -10,8 +10,6 @@ use cortex_m::peripheral::{DCB, DWT, SYST}; use embedded_hal_old::timer::{Cancel, CountDown as _, Periodic}; use void::Void; -use crate::stm32::RCC; - use crate::rcc::{self, Clocks}; use crate::time::{Hertz, MicroSecond}; @@ -214,10 +212,10 @@ where pub fn new(tim: TIM, clocks: &Clocks) -> Self { unsafe { //NOTE(unsafe) this reference will only be used for atomic writes with no side effects - let rcc = &(*RCC::ptr()); + // Enable and reset the timer peripheral - TIM::enable(rcc); - TIM::reset(rcc); + TIM::enable_unchecked(); + TIM::reset_unchecked(); } Self { diff --git a/src/usb.rs b/src/usb.rs index 2af84efe..f488aa3d 100644 --- a/src/usb.rs +++ b/src/usb.rs @@ -5,8 +5,8 @@ pub use stm32_usbd::UsbBus; use crate::gpio; +use crate::pac::USB; use crate::rcc::{Enable, Reset}; -use crate::stm32::{RCC, USB}; use core::fmt; use stm32_usbd::UsbPeripheral; @@ -56,9 +56,8 @@ unsafe impl UsbPeripheral for Peripheral