@@ -2,22 +2,22 @@ use core::{
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future:: { Future , IntoFuture } ,
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ops:: { Deref , DerefMut } ,
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pin:: Pin ,
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- sync:: atomic:: { fence, Ordering } ,
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task:: { Context , Poll } ,
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} ;
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+ use embedded_dma:: { ReadBuffer , WriteBuffer } ;
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use futures_util:: task:: AtomicWaker ;
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use crate :: interrupt;
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use crate :: stm32:: { GPDMA1 , GPDMA2 } ;
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use super :: {
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ch:: {
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- Channel , ChannelRegs , DmaChannel0 , DmaChannel1 ,
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- DmaChannel2 , DmaChannel3 , DmaChannel4 , DmaChannel5 , DmaChannel6 ,
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- DmaChannel7 , DmaChannelRef ,
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+ Channel , ChannelRegs , DmaChannel0 , DmaChannel1 , DmaChannel2 ,
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+ DmaChannel3 , DmaChannel4 , DmaChannel5 , DmaChannel6 , DmaChannel7 ,
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+ DmaChannelRef ,
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} ,
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- DmaTransfer , Error , Instance ,
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+ DmaTransfer , Error , Instance , Word ,
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} ;
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#[ allow( private_bounds) ]
@@ -32,65 +32,67 @@ where
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}
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#[ allow( private_bounds) ]
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- impl < ' a , CH > IntoFuture for DmaTransfer < ' a , CH >
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+ impl < ' a , CH , S , D > IntoFuture for DmaTransfer < ' a , CH , S , D >
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where
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CH : DmaChannel ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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{
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type Output = Result < ( ) , Error > ;
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- type IntoFuture = DmaTransferFuture < ' a , CH > ;
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+ type IntoFuture = DmaTransferFuture < ' a , CH , S , D > ;
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- fn into_future ( self ) -> DmaTransferFuture < ' a , CH > {
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+ fn into_future ( mut self ) -> DmaTransferFuture < ' a , CH , S , D > {
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self . enable_interrupts ( ) ;
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DmaTransferFuture { transfer : self }
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}
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}
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- pub struct DmaTransferFuture < ' a , CH : DmaChannel > {
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- transfer : DmaTransfer < ' a , CH > ,
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+ pub struct DmaTransferFuture < ' a , CH , S , D >
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+ where
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+ CH : DmaChannel ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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+ {
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+ transfer : DmaTransfer < ' a , CH , S , D > ,
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}
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- impl < ' a , CH > Deref for DmaTransferFuture < ' a , CH >
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+ impl < ' a , CH , S , D > Deref for DmaTransferFuture < ' a , CH , S , D >
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where
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CH : DmaChannel ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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{
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- type Target = DmaTransfer < ' a , CH > ;
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+ type Target = DmaTransfer < ' a , CH , S , D > ;
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fn deref ( & self ) -> & Self :: Target {
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& self . transfer
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}
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}
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- impl < ' a , CH > DerefMut for DmaTransferFuture < ' a , CH >
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+ impl < ' a , CH , S , D > DerefMut for DmaTransferFuture < ' a , CH , S , D >
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where
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CH : DmaChannel ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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{
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fn deref_mut ( & mut self ) -> & mut Self :: Target {
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& mut self . transfer
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}
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}
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- impl < ' a , CH > Drop for DmaTransferFuture < ' a , CH >
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+ impl < ' a , CH , S , D > Unpin for DmaTransferFuture < ' a , CH , S , D >
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where
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CH : DmaChannel ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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{
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- fn drop ( & mut self ) {
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- if self . is_running ( ) {
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- self . channel . abort ( ) ;
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- }
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-
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- self . disable_interrupts ( ) ;
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-
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- // Preserve the instruction and bus sequence of the preceding operation and
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- // the subsequent buffer access.
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- fence ( Ordering :: SeqCst ) ;
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- }
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}
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- impl < ' a , CH : DmaChannel > Unpin for DmaTransferFuture < ' a , CH > { }
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-
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- impl < ' a , CH > Future for DmaTransferFuture < ' a , CH >
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+ impl < ' a , CH , S , D > Future for DmaTransferFuture < ' a , CH , S , D >
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where
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CH : DmaChannel + ChannelWaker ,
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+ S : ReadBuffer < Word : Word > ,
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+ D : WriteBuffer < Word : Word > ,
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{
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type Output = Result < ( ) , Error > ;
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@@ -113,7 +115,7 @@ where
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{
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#[ inline( always) ]
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fn handle_interrupt ( ) {
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- let ch = Self :: new ( ) ;
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+ let mut ch = Self :: new ( ) ;
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ch. disable_transfer_interrupts ( ) ;
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ch. waker ( ) . wake ( ) ;
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}
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