WIP: Add h523 support

Author: Henrik Snöman

Cargo.toml

@@ -43,6 +43,7 @@ sdmmc2 = []                 # Only STM32H563/73 have SDMMC2
 
 rt = ["stm32h5/rt"]
 stm32h503 = ["stm32h5/stm32h503", "device-selected", "rm0492"]
+stm32h523 = ["stm32h5/stm32h523", "device-selected", "rm0481", "h523_h533"]
 stm32h562 = ["stm32h5/stm32h562", "device-selected", "rm0481", "h56x_h573"]
 stm32h563 = ["stm32h5/stm32h563", "device-selected", "rm0481", "h56x_h573", "sdmmc2", "ethernet"]
 stm32h573 = ["stm32h5/stm32h573", "device-selected", "rm0481", "h56x_h573", "otfdec", "sdmmc2", "ethernet"]
@@ -55,7 +56,8 @@ log-semihost = ["log"]
 
 [dependencies]
 cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
-stm32h5 = { package = "stm32h5-staging", version = "0.17.0" }
+stm32h5 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" }
+#stm32h5 = { package = "stm32h5-staging", version = "0.17.0" }
 fugit = "0.3.7"
 embedded-hal = "1.0.0"
 defmt = { version = "0.3.8", optional = true }

src/lib.rs

@@ -6,6 +6,7 @@
 compile_error!(
     "This crate requires one of the following device features enabled:
         stm32h503
+        stm32h523
         stm32h562
         stm32h563
         stm32h573
@@ -18,6 +19,9 @@ compile_error!("Cannot not select both rm0492 and rm0481");
 #[cfg(feature = "stm32h503")]
 pub use stm32h5::stm32h503 as stm32;
 
+#[cfg(feature = "stm32h523")]
+pub use stm32h5::stm32h523 as stm32;
+
 #[cfg(feature = "stm32h562")]
 pub use stm32h5::stm32h562 as stm32;
 

src/rcc/pll.rs

@@ -235,14 +235,17 @@ macro_rules! pll_divider_setup {
         }}
     };
 }
-
+fn foo(rcc: RCC) {
+    //rcc.pll1cfgr().modify(|_, w| w.divm1());
+    //rcc.pll1cfgr().modify(|_, w| w.pll1m());
+}
 macro_rules! pll_setup {
-    ($pllX:ident, $odd_allowed:expr) => {
+    ($X:literal, $odd_allowed:expr) => {
         paste::item! {
             /// PLL Setup
             /// Returns (Option(pllX_p_ck), Option(pllX_q_ck), Option(pllX_r_ck))
 
-            pub(super) fn [< $pllX _setup >] (
+            pub(super) fn [< pll $X _setup >] (
                 &self,
                 rcc: &RCC,
                 pll: &PllConfig,
@@ -256,20 +259,20 @@ macro_rules! pll_setup {
                     return (None, None, None);
                 }
 
-                let pll_setup = vco_setup!(pllsrc, pll, rcc, $pllX, $odd_allowed);
+                let pll_setup = vco_setup!(pllsrc, pll, rcc, [<pll $X>], $odd_allowed);
 
                 // Feedback divider. Integer only
                 let pll_x_n = pll_setup.vco_out_target / pll_setup.ref_ck;
 
                 // Write dividers
-                rcc.[< $pllX cfgr >]().modify(|_, w| unsafe {
-                    w.[< $pllX m >]()
+                rcc.[< pll $X cfgr >]().modify(|_, w| unsafe {
+                    w.[< divm $X >]()
                     .bits(pll_setup.pll_m as u8) });  // ref prescaler
 
                 // unsafe as not all values are permitted: see RM0492
                 assert!(pll_x_n >= PLL_N_MIN);
                 assert!(pll_x_n <= PLL_N_MAX);
-                rcc.[<$pllX divr>]().modify(|_, w| unsafe { w.[<$pllX n>]().bits((pll_x_n - 1) as u16) });
+                rcc.[<pll $X divr>]().modify(|_, w| unsafe { w.[< pll $X n>]().bits((pll_x_n - 1) as u16) });
 
                 let pll_x = pll_setup.pll_p.as_ref().or(pll_setup.pll_q.as_ref().or(pll_setup.pll_r.as_ref())).unwrap();
 
@@ -279,10 +282,10 @@ macro_rules! pll_setup {
                         // Calculate FRACN
                         let pll_x_fracn = calc_fracn(pll_setup.ref_ck as f32, pll_x_n as f32, pll_x.div as f32, pll_x.ck as f32);
                         //RCC_PLL1FRACR
-                        rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().set(pll_x_fracn));
+                        rcc.[<pll $X fracr>]().modify(|_, w| w.[<pll $X fracn>]().set(pll_x_fracn));
                         // Latch FRACN by resetting and setting it
-                        rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().reset() );
-                        rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set_() );
+                        rcc.[<pll $X cfgr>]().modify(|_, w| w.[< pll $X fracen>]().reset() );
+                        rcc.[<pll $X cfgr>]().modify(|_, w| w.[< pll $X fracen>]().set_() );
 
                         calc_vco_ck(pll_setup.ref_ck, pll_x_n, pll_x_fracn)
                     },
@@ -292,7 +295,7 @@ macro_rules! pll_setup {
                     },
                 };
 
-                pll_divider_setup! {($pllX, rcc, pll, vco_ck),
+                pll_divider_setup! {([<pll $X>], rcc, pll, vco_ck),
                                         p: &pll_setup.pll_p,
                                         q: &pll_setup.pll_q,
                                         r: &pll_setup.pll_r }
@@ -326,8 +329,8 @@ fn calc_vco_ck(ref_ck: u32, pll_n: u32, pll_fracn: u16) -> u32 {
 }
 
 impl Rcc {
-    pll_setup! {pll1, false}
-    pll_setup! {pll2, true}
+    pll_setup! {1, false}
+    pll_setup! {2, true}
 }
 
 #[cfg(test)]