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Update for staging PAC 0.17.0 (#28)
1 parent 64e2378 commit 86ec4c5

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7 files changed

+59
-57
lines changed

7 files changed

+59
-57
lines changed

‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ log-semihost = ["log"]
4444

4545
[dependencies]
4646
cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
47-
stm32h5 = "0.15.1"
47+
stm32h5 = { package = "stm32h5-staging", version = "0.17.0" }
4848
fugit = "0.3.7"
4949
embedded-hal = "1.0.0"
5050
defmt = { version = "0.3.8", optional = true }

‎src/gpio.rs

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -318,11 +318,9 @@ where
318318
let offset = 2 * { N };
319319

320320
unsafe {
321-
(*Gpio::<P>::ptr()).ospeedr().modify(|r, w| {
322-
w.bits(
323-
(r.bits() & !(0b11 << offset)) | ((speed as u32) << offset),
324-
)
325-
});
321+
(*Gpio::<P>::ptr())
322+
.ospeedr()
323+
.modify(|_r, w| w.ospeed(offset).bits(speed as u8));
326324
}
327325
}
328326

@@ -340,11 +338,11 @@ where
340338
/// Set the internal pull-up and pull-down resistor
341339
pub fn set_internal_resistor(&mut self, resistor: Pull) {
342340
let offset = 2 * { N };
343-
let value = resistor as u32;
341+
let value = resistor as u8;
344342
unsafe {
345-
(*Gpio::<P>::ptr()).pupdr().modify(|r, w| {
346-
w.bits((r.bits() & !(0b11 << offset)) | (value << offset))
347-
});
343+
(*Gpio::<P>::ptr())
344+
.pupdr()
345+
.modify(|_r, w| w.pupd(offset).bits(value));
348346
}
349347
}
350348

@@ -428,22 +426,26 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
428426
#[inline(always)]
429427
fn _set_high(&mut self) {
430428
// NOTE(unsafe) atomic write to a stateless register
431-
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << N)) }
429+
unsafe {
430+
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(N).set_bit());
431+
}
432432
}
433433
#[inline(always)]
434434
fn _set_low(&mut self) {
435435
// NOTE(unsafe) atomic write to a stateless register
436-
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << (16 + N))) }
436+
unsafe {
437+
(*Gpio::<P>::ptr()).bsrr().write(|w| w.br(N).set_bit());
438+
}
437439
}
438440
#[inline(always)]
439441
fn _is_set_low(&self) -> bool {
440442
// NOTE(unsafe) atomic read with no side effects
441-
unsafe { (*Gpio::<P>::ptr()).odr().read().bits() & (1 << N) == 0 }
443+
unsafe { (*Gpio::<P>::ptr()).odr().read().od(N).is_low() }
442444
}
443445
#[inline(always)]
444446
fn _is_low(&self) -> bool {
445447
// NOTE(unsafe) atomic read with no side effects
446-
unsafe { (*Gpio::<P>::ptr()).idr().read().bits() & (1 << N) == 0 }
448+
unsafe { (*Gpio::<P>::ptr()).idr().read().id(N).is_low() }
447449
}
448450
}
449451

‎src/gpio/exti.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,7 @@ where
142142
Edge::Rising => exti.rpr1().write(|w| w.bits(mask)),
143143
Edge::Falling => exti.fpr1().write(|w| w.bits(mask)),
144144
_ => panic!("Must choose a rising or falling edge"),
145-
}
145+
};
146146
}
147147
}
148148

‎src/gpio/partially_erased.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,17 +62,17 @@ impl<const P: char, MODE> PartiallyErasedPin<P, Output<MODE>> {
6262
#[inline(always)]
6363
pub fn set_high(&mut self) {
6464
// NOTE(unsafe) atomic write to a stateless register
65-
unsafe { (*Gpio::<P>::ptr()).bsrr().write(|w| w.bits(1 << self.i)) }
65+
unsafe {
66+
(*Gpio::<P>::ptr()).bsrr().write(|w| w.bs(self.i).set_bit());
67+
}
6668
}
6769

6870
/// Drives the pin low
6971
#[inline(always)]
7072
pub fn set_low(&mut self) {
7173
// NOTE(unsafe) atomic write to a stateless register
7274
unsafe {
73-
(*Gpio::<P>::ptr())
74-
.bsrr()
75-
.write(|w| w.bits(1 << (self.i + 16)))
75+
(*Gpio::<P>::ptr()).bsrr().write(|w| w.br(self.i).set_bit());
7676
}
7777
}
7878

‎src/rcc.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -685,11 +685,11 @@ impl Rcc {
685685
w.mco1sel()
686686
.variant(self.config.mco1.source)
687687
.mco1pre()
688-
.bits(mco_1_pre)
688+
.set(mco_1_pre)
689689
.mco2sel()
690690
.variant(self.config.mco2.source)
691691
.mco2pre()
692-
.bits(mco_2_pre)
692+
.set(mco_2_pre)
693693
});
694694

695695
// HSE
@@ -747,7 +747,7 @@ impl Rcc {
747747

748748
// Ensure core prescaler value is valid before future lower
749749
// core voltage
750-
while rcc.cfgr2().read().hpre().variant() != Some(hpre_bits) {}
750+
while rcc.cfgr2().read().hpre().variant() != hpre_bits {}
751751

752752
// Peripheral Clock (per_ck)
753753
rcc.ccipr5().modify(|_, w| w.ckpersel().variant(ckpersel));
@@ -805,10 +805,10 @@ impl Rcc {
805805
let cfgr2 = rcc.cfgr2().read();
806806
debug!(
807807
"CFGR2 register: HPRE={:?} PPRE1={:?} PPRE2={:?} PPRE3={:?}",
808-
cfgr2.hpre().variant().unwrap(),
809-
cfgr2.ppre1().variant().unwrap(),
810-
cfgr2.ppre2().variant().unwrap(),
811-
cfgr2.ppre3().variant().unwrap(),
808+
cfgr2.hpre().variant(),
809+
cfgr2.ppre1().variant(),
810+
cfgr2.ppre2().variant(),
811+
cfgr2.ppre3().variant(),
812812
);
813813

814814
let pll1cfgr = rcc.pll1cfgr().read();

‎src/rcc/pll.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ macro_rules! pll_divider_setup {
222222

223223
// Setup divider
224224
$rcc.[<$pllX divr>]().modify(|_, w|
225-
w.[<$pllX $d>]().variant((pll_x_d.div - 1) as u8)
225+
w.[<$pllX $d>]().set((pll_x_d.div - 1) as u8)
226226
);
227227
$rcc.[<$pllX cfgr>]().modify(|_, w| w.[<$pllX $d en>]().enabled());
228228
Some(Hertz::from_raw($vco_ck / pll_x_d.div))
@@ -262,14 +262,14 @@ macro_rules! pll_setup {
262262
let pll_x_n = pll_setup.vco_out_target / pll_setup.ref_ck;
263263

264264
// Write dividers
265-
rcc.[< $pllX cfgr >]().modify(|_, w|
265+
rcc.[< $pllX cfgr >]().modify(|_, w| unsafe {
266266
w.[< $pllX m >]()
267-
.variant(pll_setup.pll_m as u8)); // ref prescaler
267+
.bits(pll_setup.pll_m as u8) }); // ref prescaler
268268

269269
// unsafe as not all values are permitted: see RM0492
270270
assert!(pll_x_n >= PLL_N_MIN);
271271
assert!(pll_x_n <= PLL_N_MAX);
272-
rcc.[<$pllX divr>]().modify(|_, w| w.[<$pllX n>]().variant((pll_x_n - 1) as u16));
272+
rcc.[<$pllX divr>]().modify(|_, w| unsafe { w.[<$pllX n>]().bits((pll_x_n - 1) as u16) });
273273

274274
let pll_x = pll_setup.pll_p.as_ref().or(pll_setup.pll_q.as_ref().or(pll_setup.pll_r.as_ref())).unwrap();
275275

@@ -279,10 +279,10 @@ macro_rules! pll_setup {
279279
// Calculate FRACN
280280
let pll_x_fracn = calc_fracn(pll_setup.ref_ck as f32, pll_x_n as f32, pll_x.div as f32, pll_x.ck as f32);
281281
//RCC_PLL1FRACR
282-
rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().variant(pll_x_fracn));
282+
rcc.[<$pllX fracr>]().modify(|_, w| w.[<$pllX fracn>]().set(pll_x_fracn));
283283
// Latch FRACN by resetting and setting it
284284
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().reset() );
285-
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set() );
285+
rcc.[<$pllX cfgr>]().modify(|_, w| w.[< $pllX fracen>]().set_() );
286286

287287
calc_vco_ck(pll_setup.ref_ck, pll_x_n, pll_x_fracn)
288288
},

‎src/rcc/rec.rs

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -129,8 +129,8 @@ macro_rules! peripheral_reset_and_enable_control {
129129
$(
130130
$( #[ $pmeta:meta ] )*
131131
$(($NoReset:ident))? $p:ident
132-
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
133-
$([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
132+
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
133+
$([ group clk: $pk_g:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
134134
$([ fixed clk: $clk_doc_f:expr ])*
135135
),*
136136
];)+) => {
@@ -177,10 +177,10 @@ macro_rules! peripheral_reset_and_enable_control {
177177
$AXBn, $(($NoReset))* $p, [< $p:upper >], [< $p:lower >],
178178
$( $pmeta )*
179179
$(
180-
[kernel $clk: $pk $(($Variant))* $ccip $clk_doc]
180+
[kernel $clk: $pk $(($Variant))* $pk_alias $ccip $clk_doc]
181181
)*
182182
$(
183-
[group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $ccip_g $clk_doc_g )* ]
183+
[group clk: $pk_g [< $pk_g:lower >] $( $(($Variant_g))* $pk_g_alias $ccip_g $clk_doc_g )* ]
184184
)*
185185
$(
186186
[fixed clk: $clk_doc_f]
@@ -230,8 +230,8 @@ macro_rules! peripheral_reset_and_enable_control_generator {
230230
$p_lower:ident, // comments, equivalent to with the paste macro.
231231

232232
$( $pmeta:meta )*
233-
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $ccip:ident $clk_doc:expr ])*
234-
$([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $ccip_g:ident $clk_doc_g:expr )* ])*
233+
$([ kernel $clk:ident: $pk:ident $(($Variant:ident))* $pk_alias:ident $ccip:ident $clk_doc:expr ])*
234+
$([ group clk: $pk_g:ident $pk_g_lower:ident $( $(($Variant_g:ident))* $pk_g_alias:ident $ccip_g:ident $clk_doc_g:expr )* ])*
235235
$([ fixed clk: $clk_doc_f:expr ])*
236236
) => {
237237
paste::item! {
@@ -388,7 +388,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
388388
#[doc=$clk_doc]
389389
/// kernel clock source selection
390390
pub type [< $pk ClkSel >] =
391-
rcc::[< $ccip >]::[< $pk:upper SEL >];
391+
rcc::[< $ccip >]::[< $pk_alias SEL >];
392392
)*
393393
$( // Group kernel clocks
394394
impl [< $pk_g ClkSelGetter >] for $p {}
@@ -398,7 +398,7 @@ macro_rules! peripheral_reset_and_enable_control_generator {
398398
#[doc=$clk_doc_g]
399399
/// kernel clock source selection.
400400
pub type [< $pk_g ClkSel >] =
401-
rcc::[< $ccip_g >]::[< $pk_g:upper SEL >];
401+
rcc::[< $ccip_g >]::[< $pk_g_alias SEL >];
402402

403403
/// Can return
404404
#[doc=$clk_doc_g]
@@ -508,8 +508,8 @@ peripheral_reset_and_enable_control! {
508508
];
509509
#[cfg(feature = "rm0492")]
510510
AHB2, "" => [
511-
Rng [kernel clk: Rng ccipr5 "RNG"],
512-
Adc [group clk: AdcDac(Variant) ccipr5 "ADC/DAC"],
511+
Rng [kernel clk: Rng RNG ccipr5 "RNG"],
512+
Adc [group clk: AdcDac(Variant) ADCDAC ccipr5 "ADC/DAC"],
513513
Dac12 [group clk: AdcDac]
514514
];
515515

@@ -522,16 +522,16 @@ peripheral_reset_and_enable_control! {
522522
];
523523
#[cfg(feature = "rm0492")]
524524
APB1L, "" => [
525-
I3c1 [kernel clk: I3c1(Variant) ccipr4 "I3C1"],
525+
I3c1 [kernel clk: I3c1(Variant) I3C ccipr4 "I3C1"],
526526

527-
I2c1 [kernel clk: I2c1 ccipr4 "I2C1"],
528-
I2c2 [kernel clk: I2c2 ccipr4 "I2C2"],
527+
I2c1 [kernel clk: I2c1 I2C ccipr4 "I2C1"],
528+
I2c2 [kernel clk: I2c2 I2C ccipr4 "I2C2"],
529529

530-
Usart2 [kernel clk: Usart2(Variant) ccipr1 "USART2"],
531-
Usart3 [kernel clk: Usart3(Variant) ccipr1 "USART3"],
530+
Usart2 [kernel clk: Usart2(Variant) USART ccipr1 "USART2"],
531+
Usart3 [kernel clk: Usart3(Variant) USART ccipr1 "USART3"],
532532

533-
Spi2 [kernel clk: Spi2(Variant) ccipr3 "SPI2"],
534-
Spi3 [kernel clk: Spi3(Variant) ccipr3 "SPI3"],
533+
Spi2 [kernel clk: Spi2(Variant) SPI123 ccipr3 "SPI2"],
534+
Spi3 [kernel clk: Spi3(Variant) SPI123 ccipr3 "SPI3"],
535535
Opamp,
536536
Comp
537537
];
@@ -542,8 +542,8 @@ peripheral_reset_and_enable_control! {
542542
];
543543
#[cfg(feature = "rm0492")]
544544
APB1H, "" => [
545-
Lptim2 [kernel clk: Lptim2(Variant) ccipr2 "LPTIM2"],
546-
Fdcan [kernel clk: Fdcan(Variant) ccipr5 "FDCAN"]
545+
Lptim2 [kernel clk: Lptim2(Variant) LPTIM ccipr2 "LPTIM2"],
546+
Fdcan [kernel clk: Fdcan(Variant) FDCAN ccipr5 "FDCAN"]
547547
];
548548

549549
#[cfg(all())]
@@ -552,9 +552,9 @@ peripheral_reset_and_enable_control! {
552552
];
553553
#[cfg(feature = "rm0492")]
554554
APB2, "" => [
555-
Usb [kernel clk: Usb ccipr4 "USB"],
556-
Usart1 [kernel clk: Usart1(Variant) ccipr1 "USART1"],
557-
Spi1 [kernel clk: Spi1(Variant) ccipr3 "SPI1"]
555+
Usb [kernel clk: Usb USB ccipr4 "USB"],
556+
Usart1 [kernel clk: Usart1(Variant) USART ccipr1 "USART1"],
557+
Spi1 [kernel clk: Spi1(Variant) SPI123 ccipr3 "SPI1"]
558558
];
559559

560560
#[cfg(all())]
@@ -564,9 +564,9 @@ peripheral_reset_and_enable_control! {
564564
];
565565
#[cfg(feature = "rm0492")]
566566
APB3, "" => [
567-
I3c2 [kernel clk: I3c2(Variant) ccipr4 "I3C2"],
568-
LpTim1 [kernel clk: LpTim1(Variant) ccipr2 "LPTIM1"],
569-
LpUart1 [kernel clk: LpUart1(Variant) ccipr3 "LPUART1"]
567+
I3c2 [kernel clk: I3c2(Variant) I3C ccipr4 "I3C2"],
568+
LpTim1 [kernel clk: LpTim1(Variant) LPTIM ccipr2 "LPTIM1"],
569+
LpUart1 [kernel clk: LpUart1(Variant) USART ccipr3 "LPUART1"]
570570
];
571571

572572
}

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