spi: Enable SPI DMA transfers

Author: astapleton

examples/spi-dma.rs

@@ -0,0 +1,97 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+mod utilities;
+
+use core::mem::MaybeUninit;
+
+use cortex_m_rt::entry;
+use cortex_m_semihosting::debug;
+use stm32h5xx_hal::{
+    pac,
+    prelude::*,
+    spi::{self, Config as SpiConfig, Spi, dma::DuplexDmaTransfer},
+};
+
+static mut SOURCE_BYTES: MaybeUninit<[u8; 40]> = MaybeUninit::uninit();
+static mut DEST_BYTES: MaybeUninit<[u8; 40]> = MaybeUninit::zeroed();
+
+fn u8_to_u8_sequential() -> (&'static [u8; 40], &'static mut [u8; 40]) {
+    let buf: &mut [MaybeUninit<u8>; 40] = unsafe {
+        &mut *(core::ptr::addr_of_mut!(SOURCE_BYTES)
+            as *mut [MaybeUninit<u8>; 40])
+    };
+
+    for (i, value) in buf.iter_mut().enumerate() {
+        unsafe {
+            value.as_mut_ptr().write(i as u8);
+        }
+    }
+    #[allow(static_mut_refs)] // TODO: Fix this
+    let src = unsafe { SOURCE_BYTES.assume_init_ref() };
+
+    let dest =
+        unsafe { (*core::ptr::addr_of_mut!(DEST_BYTES)).assume_init_mut() };
+
+    dest.fill(0);
+
+    (src, dest)
+}
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Constrain and Freeze power
+    log::info!("Setup PWR...                  ");
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = pwr.freeze();
+
+    // Constrain and Freeze clock
+    log::info!("Setup RCC...                  ");
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc
+        .sys_ck(192.MHz())
+        .pll1_q_ck(64.MHz())
+        .freeze(pwrcfg, &dp.SBS);
+
+    // Acquire the GPIOB peripheral. This also enables the clock for
+    // GPIOB in the RCC register.
+    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
+
+    let sck = gpiob.pb13.into_alternate();
+    let miso = gpiob.pb14.into_alternate();
+    let mosi = gpiob.pb15.into_alternate();
+
+    log::info!("stm32h5xx-hal example - SPI DMA");
+
+    // Initialise the SPI peripheral.
+    let mut spi: Spi<_, u8> = dp.SPI2.spi(
+        (sck, miso, mosi),
+        SpiConfig::new(spi::MODE_0),
+        1.MHz(),
+        ccdr.peripheral.SPI2,
+        &ccdr.clocks,
+    );
+
+    let (source_buf, dest_buf) = u8_to_u8_sequential();
+
+    let channels = dp.GPDMA1.channels(ccdr.peripheral.GPDMA1);
+    let tx_ch = channels.0;
+    let rx_ch = channels.1;
+
+    let mut transfer = DuplexDmaTransfer::new(&mut spi, tx_ch, rx_ch, source_buf, dest_buf);
+    transfer.start().unwrap();
+    transfer.wait_for_complete().unwrap();
+    let (_, _, source_buf, dest_buf) = transfer.free().unwrap();
+
+    assert_eq!(source_buf, dest_buf);
+
+    log::info!("Success!");
+    loop {
+        debug::exit(debug::EXIT_SUCCESS)
+    }
+}

src/spi.rs

@@ -141,13 +141,15 @@ pub use embedded_hal::spi::{
     Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
 };
 
+use crate::gpdma::Error as DmaError;
 use crate::rcc::{CoreClocks, ResetEnable};
 use crate::stm32::spi1;
 
 use crate::time::Hertz;
 use spi1::{cfg1::MBR, cfg2::LSBFRST, cfg2::SSIOP};
 
 mod config;
+pub mod dma;
 mod hal;
 pub mod nonblocking;
 mod spi_def;
@@ -182,6 +184,14 @@ pub enum Error {
     /// Caller makes invalid call (e.g. write in SimplexReceiver mode, or read in
     /// SimplexTransmitter)
     InvalidOperation,
+    /// A DMA error occurred during processing
+    DmaError(DmaError)
+}
+
+impl From<DmaError> for Error {
+    fn from(error: DmaError) -> Self {
+        Error::DmaError(error)
+    }
 }
 
 pub trait Pins<SPI> {
@@ -252,6 +262,12 @@ pub trait Instance:
 
     #[doc(hidden)]
     fn rec() -> Self::Rec;
+
+    #[doc(hidden)]
+    fn tx_dma_request() -> u8;
+
+    #[doc(hidden)]
+    fn rx_dma_request() -> u8;
 }
 
 pub trait Word: Copy + Default + 'static + crate::Sealed {
@@ -564,6 +580,29 @@ impl<SPI: Instance, W: Word> Inner<SPI, W> {
         let _ = self.spi.sr().read();
     }
 
+    /// Disable DMA for both Rx and Tx
+    #[inline]
+    pub fn enable_tx_dma(&self) {
+        self.spi.cfg1().modify(|_, w| w.txdmaen().disabled());
+    }
+
+    /// Disable DMA for both Rx and Tx
+    #[inline]
+    pub fn enable_rx_dma(&self) {
+        self.spi.cfg1().modify(|_, w| w.rxdmaen().disabled());
+    }
+
+    /// Disable DMA for both Rx and Tx
+    #[inline]
+    pub fn disable_dma(&self) {
+        self.spi.cfg1().modify(|_, w| w.rxdmaen().disabled().txdmaen().disabled());
+    }
+
+    #[inline]
+    pub fn start_transfer(&self) {
+        self.spi.cr1().modify(|_, w| w.cstart().started());
+    }
+
     /// Read a single word from the receive data register
     #[inline(always)]
     fn read_data_reg(&mut self) -> W {

src/spi/dma.rs

@@ -0,0 +1,222 @@
+use core::marker::PhantomData;
+
+use embedded_dma::{ReadBuffer, WriteBuffer};
+
+use crate::gpdma::{
+    config::{Config as DmaConfig, MemoryToPeripheral, PeripheralToMemory},
+    Channel, Transfer as DmaTransfer, Word,
+};
+
+use super::{Error, FrameSize, Instance, Spi};
+
+pub struct DmaRx<SPI, W> {
+    _spi: PhantomData<SPI>,
+    _word: PhantomData<W>,
+}
+
+impl<SPI, W> DmaRx<SPI, W> {
+    fn new() -> Self {
+        Self {
+            _spi: PhantomData,
+            _word: PhantomData,
+        }
+    }
+}
+
+unsafe impl<SPI: Instance, W: FrameSize> ReadBuffer for DmaRx<SPI, W> {
+    type Word = W;
+
+    unsafe fn read_buffer(&self) -> (*const Self::Word, usize) {
+        ((*SPI::ptr()).rxdr().as_ptr() as *const W, 1)
+    }
+}
+
+pub struct DmaTx<SPI, W> {
+    _spi: PhantomData<SPI>,
+    _word: PhantomData<W>,
+}
+
+impl<SPI, W> DmaTx<SPI, W> {
+    fn new() -> Self {
+        Self {
+            _spi: PhantomData,
+            _word: PhantomData,
+        }
+    }
+}
+
+unsafe impl<SPI: Instance, W: FrameSize> WriteBuffer for DmaTx<SPI, W> {
+    type Word = W;
+
+    unsafe fn write_buffer(&mut self) -> (*mut Self::Word, usize) {
+        ((*SPI::ptr()).txdr().as_ptr() as *mut W, 1)
+    }
+}
+
+pub struct RxDmaTransfer<SPI, W: FrameSize, CH, D> {
+    spi: Spi<SPI, W>,
+    transfer: DmaTransfer<CH, DmaRx<SPI, W>, D, PeripheralToMemory>,
+}
+
+impl<SPI, W, CH, D> RxDmaTransfer<SPI, W, CH, D>
+where
+    SPI: Instance,
+    W: FrameSize + Word,
+    CH: Channel,
+    D: WriteBuffer<Word = W>,
+{
+    pub fn new(spi: Spi<SPI, W>, channel: CH, destination: D) -> Self {
+        let config = DmaConfig::new().with_request(SPI::rx_dma_request());
+        let source = DmaRx::new();
+        let transfer = DmaTransfer::peripheral_to_memory(
+            config,
+            channel,
+            source,
+            destination,
+        );
+        Self { spi, transfer }
+    }
+
+    pub fn start(&mut self) -> Result<(), crate::gpdma::Error> {
+        self.spi.enable_rx_dma();
+        self.transfer.start_with(|_, _| {
+            self.spi.enable();
+            self.spi.start_transfer();
+        })
+    }
+}
+
+pub struct TxDmaTransfer<SPI, W: FrameSize, CH, S> {
+    spi: Spi<SPI, W>,
+    transfer: DmaTransfer<CH, S, DmaTx<SPI, W>, MemoryToPeripheral>,
+}
+
+impl<SPI, W, CH, S> TxDmaTransfer<SPI, W, CH, S>
+where
+    SPI: Instance,
+    W: FrameSize + Word,
+    CH: Channel,
+    S: ReadBuffer<Word = W>,
+{
+    pub fn new(spi: Spi<SPI, W>, channel: CH, source: S) -> Self {
+        let config = DmaConfig::new().with_request(SPI::tx_dma_request());
+        let destination = DmaTx::new();
+        let transfer = DmaTransfer::memory_to_peripheral(
+            config,
+            channel,
+            source,
+            destination,
+        );
+        Self { spi, transfer }
+    }
+
+    pub fn start(&mut self) -> Result<(), crate::gpdma::Error> {
+        self.transfer.start_with(|_, _| {
+            self.spi.enable_tx_dma();
+            self.spi.enable();
+            self.spi.start_transfer();
+        })
+    }
+}
+
+pub struct DuplexDmaTransfer<'a, SPI, W: FrameSize, TX, RX, S, D> {
+    spi: &'a mut Spi<SPI, W>,
+    tx_transfer: DmaTransfer<TX, S, DmaTx<SPI, W>, MemoryToPeripheral>,
+    rx_transfer: DmaTransfer<RX, DmaRx<SPI, W>, D, PeripheralToMemory>,
+}
+
+impl<'a, SPI, W, RX, TX, S, D> DuplexDmaTransfer<'a, SPI, W, TX, RX, S, D>
+where
+    SPI: Instance,
+    W: FrameSize + Word,
+    TX: Channel,
+    RX: Channel,
+    S: ReadBuffer<Word = W>,
+    D: WriteBuffer<Word = W>,
+{
+    pub fn new(
+        spi: &'a mut Spi<SPI, W>,
+        tx_channel: TX,
+        rx_channel: RX,
+        source: S,
+        destination: D,
+    ) -> Self {
+        let tx_config = DmaConfig::new().with_request(SPI::tx_dma_request());
+        let tx_destination = DmaTx::new();
+        let tx_transfer = DmaTransfer::memory_to_peripheral(
+            tx_config,
+            tx_channel,
+            source,
+            tx_destination,
+        );
+        let rx_source = DmaRx::new();
+        let rx_config = DmaConfig::new().with_request(SPI::rx_dma_request());
+        let rx_transfer = DmaTransfer::peripheral_to_memory(
+            rx_config,
+            rx_channel,
+            rx_source,
+            destination,
+        );
+        Self {
+            spi,
+            tx_transfer,
+            rx_transfer,
+        }
+    }
+
+    pub fn start(&mut self) -> Result<(), Error> {
+        self.spi.enable_rx_dma();
+        self.rx_transfer.start()?;
+        self.tx_transfer.start_with(|_, _| {
+            self.spi.enable_tx_dma();
+            self.spi.enable();
+            self.spi.start_transfer();
+        })?;
+        Ok(())
+    }
+
+    pub fn is_dma_complete(&self) -> Result<bool, Error> {
+        let complete = self.tx_transfer.is_transfer_complete()?
+            && self.rx_transfer.is_transfer_complete()?;
+        Ok(complete)
+    }
+
+    pub fn wait_for_complete(&mut self) -> Result<(), Error> {
+        while !self.is_dma_complete()? {}
+        self.spi.end_transaction();
+        self.spi.disable_dma();
+        Ok(())
+    }
+
+    pub fn end_transfer(&mut self) {
+        self.spi.end_transaction();
+        self.spi.disable_dma();
+    }
+
+    pub fn free(self) -> Result<(TX, RX, S, D), Error> {
+        let (tx, s, _) = self.tx_transfer.free()?;
+        let (rx, _, d) = self.rx_transfer.free()?;
+        Ok((tx, rx, s, d))
+    }
+}
+
+type DuplexInplaceDmaTransfer<'a, SPI, W, TX, RX> =
+    DuplexDmaTransfer<'a, SPI, W, TX, RX, &'static [W], &'static mut [W]>;
+
+impl<SPI: Instance, W: FrameSize + Word> Spi<SPI, W> {
+    pub fn dma_transfer_inplace<TX: Channel, RX: Channel>(
+        &mut self,
+        buffer: &'static mut [W],
+        tx_channel: TX,
+        rx_channel: RX,
+    ) -> Result<DuplexInplaceDmaTransfer<SPI, W, TX, RX>, Error> {
+        // Note (unsafe): Data will be read from the start of the buffer before data is written
+        // to those locations just like for blocking non-DMA in-place transfers
+        let source = unsafe { *(buffer.as_ptr() as *const &[W]) };
+        let mut transfer = DuplexDmaTransfer::new(
+            self, tx_channel, rx_channel, source, buffer,
+        );
+        transfer.start()?;
+        Ok(transfer)
+    }
+}