Fix some clippy warnings

Author: usbalbin

src/rcc.rs

@@ -413,7 +413,7 @@ macro_rules! ppre_calculate {
                 .unwrap_or($hclk);
 
             // Calculate suitable divider
-            let ($bits, $ppre) = match ($hclk + $pclk - 1) / $pclk
+            let ($bits, $ppre) = match $hclk.div_ceil($pclk)
             {
                 0 => unreachable!(),
                 1 => (PPRE::Div1, 1 as u8),
@@ -618,7 +618,7 @@ impl Rcc {
 
         // Estimate divisor
         let (hpre_bits, hpre_div) =
-            match (sys_ck.raw() + rcc_hclk - 1) / rcc_hclk {
+            match sys_ck.raw().div_ceil(rcc_hclk) {
                 0 => unreachable!(),
                 1 => (HPRE::Div1, 1),
                 2 => (HPRE::Div2, 2),

src/rcc/mco.rs

@@ -44,7 +44,7 @@ macro_rules! calculate_prescaler {
             // Running?
             if let Some(freq) = self.frequency {
                 // Calculate prescaler
-                let prescaler = match (in_ck + freq - 1) / freq {
+                let prescaler = match in_ck.div_ceil(freq) {
                     0 => unreachable!(),
                     x @ 1..=15 => x,
                     _ => {

src/rcc/pll.rs

@@ -129,8 +129,7 @@ fn vco_output_divider_setup(
     let vco_out_target = max_output * min_div;
 
     let vco_out_target = if (vco_out_target / min_output) > PLL_OUT_DIV_MAX {
-        let f = ((vco_out_target / min_output) + PLL_OUT_DIV_MAX - 1)
-            / PLL_OUT_DIV_MAX;
+        let f = (vco_out_target / min_output).div_ceil(PLL_OUT_DIV_MAX);
         vco_out_target / f
     } else {
         vco_out_target
@@ -153,7 +152,7 @@ fn vco_output_divider_setup(
     // Input divisor, resulting in a reference clock in the
     // range 2 to 16 MHz.
     let pll_x_m_min =
-        (pllsrc + range.input_range.end() - 1) / range.input_range.end();
+        pllsrc.div_ceil(*range.input_range.end());
     let pll_x_m_max = (pllsrc / range.input_range.start()).min(PLL_M_MAX);
 
     // Iterative search for the lowest m value that minimizes