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richardeoinrichardeoin
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stringify consumer name for error message
1 parent ddfd29f commit 0a8c9a3

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8 files changed

+68
-25
lines changed

8 files changed

+68
-25
lines changed

‎src/pwm.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,7 +1052,7 @@ macro_rules! tim_hal {
10521052
prec.enable().reset();
10531053

10541054
let clk = $TIMX::get_clk(clocks)
1055-
.expect("$TIMX: Input clock not running!");
1055+
.expect(concat!(stringify!($TIMX), ": Input clock not running!"));
10561056

10571057
let (period, prescale) = match $bits {
10581058
16 => calculate_frequency_16bit(clk, freq, Alignment::Left),
@@ -1096,7 +1096,7 @@ macro_rules! tim_hal {
10961096
prec.enable().reset();
10971097

10981098
let clk = $TIMX::get_clk(clocks)
1099-
.expect("$TIMX: Input clock not running!")
1099+
.expect(concat!(stringify!($TIMX), ": Input clock not running!"))
11001100
.0;
11011101

11021102
PwmBuilder {
@@ -1646,7 +1646,8 @@ macro_rules! lptim_hal {
16461646
prec.enable().reset();
16471647

16481648
let clk = $TIMX::get_clk(clocks)
1649-
.expect("$TIMX: Input clock not running").0;
1649+
.expect(concat!(stringify!($TIMX), ": Input clock not running!"))
1650+
.0;
16501651
let freq = freq.0;
16511652
let reload = clk / freq;
16521653
assert!(reload < 128 * (1 << 16));

‎src/sai/i2s.rs

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -467,7 +467,9 @@ macro_rules! i2s {
467467
(ker_ck_a.0) / (audio_freq.0 * clock_ratio);
468468
let mclk_div: u8 = mclk_div
469469
.try_into()
470-
.expect("$SAIX A: Kernel clock is out of range for required MCLK");
470+
.expect(concat!(stringify!($SAIX),
471+
" A: Kernel clock is out of range for required MCLK"
472+
));
471473

472474
// Configure SAI peripheral
473475
let mut per_sai = Sai {
@@ -532,7 +534,10 @@ macro_rules! i2s {
532534
(ker_ck_a.0) / (audio_freq.0 * clock_ratio);
533535
let mclk_div: u8 = mclk_div
534536
.try_into()
535-
.expect("$SAIX B: Kernel clock is out of range for required MCLK");
537+
.expect(concat!(stringify!($SAIX),
538+
" B: Kernel clock is out of range for required MCLK"
539+
));
540+
536541

537542
// Configure SAI peripheral
538543
let mut per_sai = Sai {

‎src/sai/mod.rs

Lines changed: 24 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -72,17 +72,25 @@ macro_rules! impl_sai_ker_ck {
7272
fn sai_a_ker_ck(prec: &Self::Rec, clocks: &CoreClocks) -> Hertz {
7373
match prec.$get_mux_A() {
7474
Some(rec::$AccessA::PLL1_Q) => {
75-
clocks.pll1_q_ck().expect("$SAIX A: PLL1_Q must be enabled")
75+
clocks.pll1_q_ck().expect(
76+
concat!(stringify!($SAIX), " A: PLL1_Q must be enabled")
77+
)
7678
}
7779
Some(rec::$AccessA::PLL2_P) => {
78-
clocks.pll2_p_ck().expect("$SAIX A: PLL2_P must be enabled")
80+
clocks.pll2_p_ck().expect(
81+
concat!(stringify!($SAIX), " A: PLL2_P must be enabled")
82+
)
7983
}
8084
Some(rec::$AccessA::PLL3_P) => {
81-
clocks.pll3_p_ck().expect("$SAIX A: PLL3_P must be enabled")
85+
clocks.pll3_p_ck().expect(
86+
concat!(stringify!($SAIX), " A: PLL3_P must be enabled")
87+
)
8288
}
8389
Some(rec::$AccessA::I2S_CKIN) => unimplemented!(),
8490
Some(rec::$AccessA::PER) => {
85-
clocks.per_ck().expect("$SAIX A: PER clock must be enabled")
91+
clocks.per_ck().expect(
92+
concat!(stringify!($SAIX), " A: PER clock must be enabled")
93+
)
8694
}
8795
_ => unreachable!(),
8896
}
@@ -91,17 +99,25 @@ macro_rules! impl_sai_ker_ck {
9199
fn sai_b_ker_ck(prec: &Self::Rec, clocks: &CoreClocks) -> Hertz {
92100
match prec.$get_mux_B() {
93101
Some(rec::$AccessB::PLL1_Q) => {
94-
clocks.pll1_q_ck().expect("$SAIX B: PLL1_Q must be enabled")
102+
clocks.pll1_q_ck().expect(
103+
concat!(stringify!($SAIX), " B: PLL1_Q must be enabled")
104+
)
95105
}
96106
Some(rec::$AccessB::PLL2_P) => {
97-
clocks.pll2_p_ck().expect("$SAIX B: PLL2_P must be enabled")
107+
clocks.pll2_p_ck().expect(
108+
concat!(stringify!($SAIX), " B: PLL2_P must be enabled")
109+
)
98110
}
99111
Some(rec::$AccessB::PLL3_P) => {
100-
clocks.pll3_p_ck().expect("$SAIX B: PLL3_P must be enabled")
112+
clocks.pll3_p_ck().expect(
113+
concat!(stringify!($SAIX), " B: PLL3_P must be enabled")
114+
)
101115
}
102116
Some(rec::$AccessB::I2S_CKIN) => unimplemented!(),
103117
Some(rec::$AccessB::PER) => {
104-
clocks.per_ck().expect("$SAIX B: PER clock must be enabled")
118+
clocks.per_ck().expect(
119+
concat!(stringify!($SAIX), " B: PER clock must be enabled")
120+
)
105121
}
106122
_ => unreachable!(),
107123
}

‎src/sai/pdm.rs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,10 @@ macro_rules! hal {
253253
let ker_ck_a = $SAIX::sai_a_ker_ck(&prec, clocks);
254254
let kernel_clock_divider: u8 = (ker_ck_a.0 / mclk_a_hz)
255255
.try_into()
256-
.expect("$SAIX: Kernel clock is out of range for required MCLK");
256+
.expect(concat!(stringify!($SAIX),
257+
": Kernel clock is out of range for required MCLK"
258+
));
259+
257260

258261
// Configure SAI peripeheral
259262
let mut s = Sai {

‎src/sdmmc.rs

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -455,10 +455,14 @@ macro_rules! sdmmc {
455455
let hclk = clocks.hclk();
456456
let ker_ck = match prec.get_kernel_clk_mux() {
457457
rec::SdmmcClkSel::PLL1_Q => {
458-
clocks.pll1_q_ck().expect("SDMMC: PLL1_Q must be enabled")
458+
clocks.pll1_q_ck().expect(
459+
concat!(stringify!($SDMMCX), ": PLL1_Q must be enabled")
460+
)
459461
}
460462
rec::SdmmcClkSel::PLL2_R => {
461-
clocks.pll2_r_ck().expect("SDMMC: PLL2_R must be enabled")
463+
clocks.pll2_r_ck().expect(
464+
concat!(stringify!($SDMMCX), ": PLL2_R must be enabled")
465+
)
462466
}
463467
};
464468

‎src/serial.rs

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -978,16 +978,24 @@ macro_rules! usart_sel {
978978
match ccip.$sel().variant() {
979979
Some($SEL::$PCLK) => clocks.$pclk(),
980980
Some($SEL::PLL2_Q) => {
981-
clocks.pll2_q_ck().expect("$USARTX: PLL2_Q must be enabled")
981+
clocks.pll2_q_ck().expect(
982+
concat!(stringify!($USARTX), ": PLL2_Q must be enabled")
983+
)
982984
}
983985
Some($SEL::PLL3_Q) => {
984-
clocks.pll3_q_ck().expect("$USARTX: PLL3_Q must be enabled")
986+
clocks.pll3_q_ck().expect(
987+
concat!(stringify!($USARTX), ": PLL3_Q must be enabled")
988+
)
985989
}
986990
Some($SEL::HSI_KER) => {
987-
clocks.hsi_ck().expect("$USARTX: HSI clock must be enabled")
991+
clocks.hsi_ck().expect(
992+
concat!(stringify!($USARTX), ": HSI clock must be enabled")
993+
)
988994
}
989995
Some($SEL::CSI_KER) => {
990-
clocks.csi_ck().expect("$USARTX: CSI clock must be enabled")
996+
clocks.csi_ck().expect(
997+
concat!(stringify!($USARTX), ": CSI clock must be enabled")
998+
)
991999
}
9921000
Some($SEL::LSE) => unimplemented!(),
9931001
_ => unreachable!(),

‎src/timer.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ macro_rules! hal {
300300
prec.enable().reset();
301301

302302
let clk = $TIMX::get_clk(clocks)
303-
.expect("$TIMX: Input clock not running!").0;
303+
.expect(concat!(stringify!($TIMX), ": Input clock not running!")).0;
304304

305305
Timer {
306306
clk,
@@ -591,7 +591,7 @@ macro_rules! lptim_hal {
591591
prec.enable().reset();
592592

593593
let clk = $TIMX::get_clk(clocks)
594-
.expect("Timer input clock not running!").0;
594+
.expect(concat!(stringify!($TIMX), ": Input clock not running!")).0;
595595

596596
let mut timer = LpTimer {
597597
clk,

‎src/xspi/mod.rs

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -448,13 +448,19 @@ mod common {
448448
match ccipr.$ccip().variant() {
449449
ccipr::[< $ccip:upper _A >]::RCC_HCLK3 => clocks.hclk(),
450450
ccipr::[< $ccip:upper _A >]::PLL1_Q => {
451-
clocks.pll1_q_ck().expect("$peripheral: PLL1_Q must be enabled")
451+
clocks.pll1_q_ck().expect(
452+
concat!(stringify!($peripheral), ": PLL1_Q must be enabled")
453+
)
452454
}
453455
ccipr::[< $ccip:upper _A >]::PLL2_R => {
454-
clocks.pll2_r_ck().expect("$peripheral: PLL2_R must be enabled")
456+
clocks.pll2_r_ck().expect(
457+
concat!(stringify!($peripheral), ": PLL2_R must be enabled")
458+
)
455459
}
456460
ccipr::[< $ccip:upper _A >]::PER => {
457-
clocks.per_ck().expect("$peripheral: PER clock must be enabled")
461+
clocks.per_ck().expect(
462+
concat!(stringify!($peripheral), ": PER clock must be enabled")
463+
)
458464
}
459465
}
460466
}

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