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qei pins
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3 files changed

+84
-203
lines changed

3 files changed

+84
-203
lines changed

‎src/i2c.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -288,7 +288,7 @@ impl<I2C: Instance> I2c<I2C> {
288288
prec: I2C::Rec,
289289
clocks: &CoreClocks,
290290
) -> Self {
291-
let _pins = (pins.0.into(), pins.1.into());
291+
let _pins: (I2C::Scl, I2C::Sda) = (pins.0.into(), pins.1.into());
292292
Self::new_unchecked(i2c, frequency, prec, clocks)
293293
}
294294
/// Create and initialise a new I2C peripheral.

‎src/pwm.rs

Lines changed: 58 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,10 @@
1717
//! ```rust
1818
//! let gpioa = ..; // Set up and split GPIOA
1919
//! let pins = (
20-
//! gpioa.pa8.into_alternate_af1(),
21-
//! gpioa.pa9.into_alternate_af1(),
22-
//! gpioa.pa10.into_alternate_af1(),
23-
//! gpioa.pa11.into_alternate_af1(),
20+
//! gpioa.pa8.into_alternate(),
21+
//! gpioa.pa9.into_alternate(),
22+
//! gpioa.pa10.into_alternate(),
23+
//! gpioa.pa11.into_alternate(),
2424
//! );
2525
//! ```
2626
//!
@@ -56,10 +56,10 @@
5656
//! ```rust
5757
//! let gpioa = ..; // Set up and split GPIOA
5858
//! let pins = (
59-
//! gpioa.pa8.into_alternate_af1(),
60-
//! gpioa.pa9.into_alternate_af1(),
61-
//! gpioa.pa10.into_alternate_af1(),
62-
//! gpioa.pa11.into_alternate_af1(),
59+
//! gpioa.pa8.into_alternate(),
60+
//! gpioa.pa9.into_alternate(),
61+
//! gpioa.pa10.into_alternate(),
62+
//! gpioa.pa11.into_alternate(),
6363
//! );
6464
//! ```
6565
//!
@@ -203,6 +203,10 @@ pub trait FaultPins<TIM> {
203203
const INPUT: BreakInput;
204204
}
205205

206+
pub trait PinCh<const C: u8> {
207+
type Pin;
208+
}
209+
206210
/// Channel wrapper
207211
pub struct Ch<const C: u8>;
208212
impl<const C: u8> Ch<C> {
@@ -1388,10 +1392,14 @@ pub trait PwmPinEnable {
13881392
// Implement PwmPin for timer channels
13891393
macro_rules! tim_pin_hal {
13901394
// Standard pins (no complementary functionality)
1391-
($TIMX:ty, $typ:ty: $(
1392-
($CH:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+
1395+
($TIMX:ty, $tim:ident, $typ:ty: $(
1396+
($CH:ident, $Ch:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+
13931397
) => {
13941398
$(
1399+
impl PinCh<$CH> for $TIMX {
1400+
type Pin = gpio::alt::$tim::$Ch;
1401+
}
1402+
13951403
impl<COMP> hal::PwmPin for Pwm<$TIMX, $CH, COMP>
13961404
where Pwm<$TIMX, $CH, COMP>: PwmPinEnable {
13971405
type Duty = $typ;
@@ -1561,73 +1569,73 @@ macro_rules! tim_pin_hal {
15611569

15621570
// Dual channel timers
15631571
tim_pin_hal! {
1564-
pac::TIM12, u16:
1565-
(C1, ccmr1_output, oc1pe, oc1m),
1566-
(C2, ccmr1_output, oc2pe, oc2m),
1572+
pac::TIM12, tim12, u16:
1573+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1574+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
15671575
}
15681576
tim_pin_hal! {
1569-
pac::TIM15, u16:
1570-
(C1, ccmr1_output, oc1pe, oc1m),
1571-
(C2, ccmr1_output, oc2pe, oc2m),
1577+
pac::TIM15, tim15, u16:
1578+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1579+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
15721580
}
15731581

15741582
// Single channel timers
15751583
tim_pin_hal! {
1576-
pac::TIM13, u16: (C1, ccmr1_output, oc1pe, oc1m),
1584+
pac::TIM13, tim13, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
15771585
}
15781586
tim_pin_hal! {
1579-
pac::TIM14, u16: (C1, ccmr1_output, oc1pe, oc1m),
1587+
pac::TIM14, tim14, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
15801588
}
15811589
tim_pin_hal! {
1582-
pac::TIM16, u16: (C1, ccmr1_output, oc1pe, oc1m),
1590+
pac::TIM16, tim16, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
15831591
}
15841592
tim_pin_hal! {
1585-
pac::TIM17, u16: (C1, ccmr1_output, oc1pe, oc1m),
1593+
pac::TIM17, tim17, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m),
15861594
}
15871595

15881596
// Quad channel timers
15891597
tim_pin_hal! {
1590-
pac::TIM1, u16:
1591-
(C1, ccmr1_output, oc1pe, oc1m),
1592-
(C2, ccmr1_output, oc2pe, oc2m),
1593-
(C3, ccmr2_output, oc3pe, oc3m),
1594-
(C4, ccmr2_output, oc4pe, oc4m),
1598+
pac::TIM1, tim1, u16:
1599+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1600+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1601+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1602+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
15951603
}
15961604
tim_pin_hal! {
1597-
pac::TIM2, u32:
1598-
(C1, ccmr1_output, oc1pe, oc1m),
1599-
(C2, ccmr1_output, oc2pe, oc2m),
1600-
(C3, ccmr2_output, oc3pe, oc3m),
1601-
(C4, ccmr2_output, oc4pe, oc4m),
1605+
pac::TIM2, tim2, u32:
1606+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1607+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1608+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1609+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
16021610
}
16031611
tim_pin_hal! {
1604-
pac::TIM3, u16:
1605-
(C1, ccmr1_output, oc1pe, oc1m),
1606-
(C2, ccmr1_output, oc2pe, oc2m),
1607-
(C3, ccmr2_output, oc3pe, oc3m),
1608-
(C4, ccmr2_output, oc4pe, oc4m),
1612+
pac::TIM3, tim3, u16:
1613+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1614+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1615+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1616+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
16091617
}
16101618
tim_pin_hal! {
1611-
pac::TIM4, u16:
1612-
(C1, ccmr1_output, oc1pe, oc1m),
1613-
(C2, ccmr1_output, oc2pe, oc2m),
1614-
(C3, ccmr2_output, oc3pe, oc3m),
1615-
(C4, ccmr2_output, oc4pe, oc4m),
1619+
pac::TIM4, tim4, u16:
1620+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1621+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1622+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1623+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
16161624
}
16171625
tim_pin_hal! {
1618-
pac::TIM5, u32:
1619-
(C1, ccmr1_output, oc1pe, oc1m),
1620-
(C2, ccmr1_output, oc2pe, oc2m),
1621-
(C3, ccmr2_output, oc3pe, oc3m),
1622-
(C4, ccmr2_output, oc4pe, oc4m),
1626+
pac::TIM5, tim5, u32:
1627+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1628+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1629+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1630+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
16231631
}
16241632
// Quad channel timers
16251633
tim_pin_hal! {
1626-
pac::TIM8, u16:
1627-
(C1, ccmr1_output, oc1pe, oc1m),
1628-
(C2, ccmr1_output, oc2pe, oc2m),
1629-
(C3, ccmr2_output, oc3pe, oc3m),
1630-
(C4, ccmr2_output, oc4pe, oc4m),
1634+
pac::TIM8, tim8, u16:
1635+
(C1, Ch1, ccmr1_output, oc1pe, oc1m),
1636+
(C2, Ch2, ccmr1_output, oc2pe, oc2m),
1637+
(C3, Ch3, ccmr2_output, oc3pe, oc3m),
1638+
(C4, Ch4, ccmr2_output, oc4pe, oc4m),
16311639
}
16321640

16331641
// Low-power timers

‎src/qei.rs

Lines changed: 25 additions & 152 deletions
Original file line numberDiff line numberDiff line change
@@ -1,158 +1,35 @@
11
//! # Quadrature Encoder Interface
22
use crate::hal::{self, Direction};
3+
use crate::pac;
4+
use crate::pwm::{PinCh, C1, C2};
35
use crate::rcc::{rec, ResetEnable};
46

5-
use crate::gpio::{self, Alternate};
6-
7-
use crate::stm32::{TIM1, TIM8};
8-
9-
use crate::stm32::{TIM2, TIM3, TIM4, TIM5};
10-
11-
pub trait Pins<TIM> {}
12-
pub trait PinCh1<TIM> {}
13-
pub trait PinCh2<TIM> {}
14-
15-
impl<TIM, PCH1, PCH2> Pins<TIM> for (PCH1, PCH2)
16-
where
17-
PCH1: PinCh1<TIM>,
18-
PCH2: PinCh2<TIM>,
19-
{
20-
}
21-
22-
macro_rules! pins {
23-
($($TIMX:ty:
24-
CH1: [$($( #[ $pmeta1:meta ] )* $CH1:ty),*]
25-
CH2: [$($( #[ $pmeta2:meta ] )* $CH2:ty),*])+) => {
26-
$(
27-
$(
28-
$( #[ $pmeta1 ] )*
29-
impl PinCh1<$TIMX> for $CH1 {}
30-
)*
31-
$(
32-
$( #[ $pmeta2 ] )*
33-
impl PinCh2<$TIMX> for $CH2 {}
34-
)*
35-
)+
36-
}
37-
}
38-
39-
pins! {
40-
TIM1:
41-
CH1: [
42-
gpio::PA7<Alternate<1>>,
43-
gpio::PA8<Alternate<1>>,
44-
gpio::PB13<Alternate<1>>,
45-
gpio::PE8<Alternate<1>>,
46-
gpio::PE9<Alternate<1>>,
47-
#[cfg(not(feature = "stm32h7b0"))]
48-
gpio::PK0<Alternate<1>>,
49-
#[cfg(not(feature = "stm32h7b0"))]
50-
gpio::PK1<Alternate<1>>
51-
]
52-
CH2: [
53-
gpio::PA9<Alternate<1>>,
54-
gpio::PB0<Alternate<1>>,
55-
gpio::PB14<Alternate<1>>,
56-
gpio::PE10<Alternate<1>>,
57-
gpio::PE11<Alternate<1>>,
58-
#[cfg(not(feature = "stm32h7b0"))]
59-
gpio::PJ10<Alternate<1>>,
60-
#[cfg(not(feature = "stm32h7b0"))]
61-
gpio::PJ11<Alternate<1>>
62-
]
63-
64-
TIM2:
65-
CH1: [
66-
gpio::PA0<Alternate<1>>,
67-
gpio::PA5<Alternate<1>>,
68-
gpio::PA15<Alternate<1>>
69-
]
70-
CH2: [
71-
gpio::PA1<Alternate<1>>,
72-
gpio::PB3<Alternate<1>>
73-
]
74-
75-
TIM3:
76-
CH1: [
77-
gpio::PA6<Alternate<2>>,
78-
gpio::PB4<Alternate<2>>,
79-
gpio::PC6<Alternate<2>>
80-
]
81-
CH2: [
82-
gpio::PA7<Alternate<2>>,
83-
gpio::PB5<Alternate<2>>,
84-
gpio::PC7<Alternate<2>>
85-
]
86-
87-
TIM4:
88-
CH1: [
89-
gpio::PB6<Alternate<2>>,
90-
gpio::PD12<Alternate<2>>
91-
]
92-
CH2: [
93-
gpio::PB7<Alternate<2>>,
94-
gpio::PD13<Alternate<2>>
95-
]
96-
97-
TIM5:
98-
CH1: [
99-
gpio::PA0<Alternate<2>>,
100-
gpio::PH10<Alternate<2>>
101-
]
102-
CH2: [
103-
gpio::PA1<Alternate<2>>,
104-
gpio::PH11<Alternate<2>>
105-
]
106-
107-
TIM8:
108-
CH1: [
109-
gpio::PA5<Alternate<3>>,
110-
gpio::PA7<Alternate<3>>,
111-
gpio::PC6<Alternate<3>>,
112-
gpio::PH13<Alternate<3>>,
113-
#[cfg(not(feature = "rm0468"))]
114-
gpio::PI5<Alternate<3>>,
115-
#[cfg(not(feature = "stm32h7b0"))]
116-
gpio::PJ8<Alternate<3>>,
117-
#[cfg(not(feature = "stm32h7b0"))]
118-
gpio::PJ9<Alternate<3>>
119-
]
120-
CH2: [
121-
gpio::PB0<Alternate<3>>,
122-
gpio::PB14<Alternate<3>>,
123-
gpio::PC7<Alternate<3>>,
124-
gpio::PH14<Alternate<3>>,
125-
#[cfg(not(feature = "rm0468"))]
126-
gpio::PI6<Alternate<3>>,
127-
#[cfg(not(any(feature = "stm32h7b0", feature = "rm0468")))]
128-
gpio::PJ6<Alternate<3>>,
129-
#[cfg(not(feature = "stm32h7b0"))]
130-
gpio::PJ7<Alternate<3>>,
131-
#[cfg(not(feature = "stm32h7b0"))]
132-
gpio::PJ10<Alternate<3>>,
133-
#[cfg(not(feature = "stm32h7b0"))]
134-
gpio::PJ11<Alternate<3>>
135-
]
136-
137-
}
138-
1397
/// Hardware quadrature encoder interface peripheral
1408
pub struct Qei<TIM> {
1419
tim: TIM,
14210
}
14311

144-
pub trait QeiExt<TIM> {
12+
pub trait QeiExt: Sized + PinCh<C1> + PinCh<C2> {
14513
type Rec: ResetEnable;
14614

147-
fn qei<PINS>(self, _pins: PINS, prec: Self::Rec) -> Qei<TIM>
148-
where
149-
PINS: Pins<TIM>;
15+
fn qei(
16+
self,
17+
pins: (
18+
impl Into<<Self as PinCh<C1>>::Pin>,
19+
impl Into<<Self as PinCh<C2>>::Pin>,
20+
),
21+
prec: Self::Rec,
22+
) -> Qei<Self> {
23+
let _pins: (<Self as PinCh<C1>>::Pin, <Self as PinCh<C2>>::Pin) =
24+
(pins.0.into(), pins.1.into());
25+
Self::qei_unchecked(self, prec)
26+
}
15027

151-
fn qei_unchecked(self, prec: Self::Rec) -> Qei<TIM>;
28+
fn qei_unchecked(self, prec: Self::Rec) -> Qei<Self>;
15229
}
15330

15431
macro_rules! tim_hal {
155-
($($TIM:ident: ($tim:ident, $Rec:ident, $bits:ident),)+) => {
32+
($($TIM:ty: ($tim:ident, $Rec:ident, $bits:ident),)+) => {
15633
$(
15734
impl Qei<$TIM> {
15835
/// Configures a TIM peripheral as a quadrature
@@ -198,14 +75,10 @@ macro_rules! tim_hal {
19875
}
19976
}
20077

201-
impl QeiExt<$TIM> for $TIM {
78+
impl QeiExt for $TIM {
20279
type Rec = rec::$Rec;
20380

204-
fn qei<PINS>(self, _pins: PINS, prec: Self::Rec) -> Qei<$TIM> {
205-
Qei::$tim(self, prec)
206-
}
207-
208-
fn qei_unchecked(self, prec: Self::Rec) -> Qei<$TIM> {
81+
fn qei_unchecked(self, prec: Self::Rec) -> Qei<Self> {
20982
Qei::$tim(self, prec)
21083
}
21184
}
@@ -231,10 +104,10 @@ macro_rules! tim_hal {
231104
}
232105

233106
tim_hal! {
234-
TIM1: (tim1, Tim1, u16),
235-
TIM8: (tim8, Tim8, u16),
236-
TIM2: (tim2, Tim2, u32),
237-
TIM3: (tim3, Tim3, u16),
238-
TIM4: (tim4, Tim4, u16),
239-
TIM5: (tim5, Tim5, u32),
107+
pac::TIM1: (tim1, Tim1, u16),
108+
pac::TIM8: (tim8, Tim8, u16),
109+
pac::TIM2: (tim2, Tim2, u32),
110+
pac::TIM3: (tim3, Tim3, u16),
111+
pac::TIM4: (tim4, Tim4, u16),
112+
pac::TIM5: (tim5, Tim5, u32),
240113
}

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