consolidate setup

Author: x37v

src/xspi/mod.rs

@@ -460,6 +460,9 @@ mod common {
                         w.dcyc().bits(dummy_cycles).instruction().bits(ir).fmode().bits(fmode)
                     };
 
+                    #[cfg(any(feature = "rm0455", feature = "rm0468"))]
+                    let w = w.isize().bits(instruction.size());
+
                     w.imode()
                         .bits(imode)
                         .admode()
@@ -479,6 +482,25 @@ mod common {
                     self.rb.tcr.write(|w| unsafe { w.dcyc().bits(dummy_cycles) });
                     self.rb.cr.modify(|_, w| unsafe { w.fmode().bits(fmode) });
                 }
+
+                // Write alternate-bytes
+                self.rb.abr.write(|w| unsafe {
+                    w.alternate().bits(alternate_bytes.bits())
+                });
+
+                #[cfg(any(feature = "rm0455", feature = "rm0468"))]
+                if instruction != XspiWord::None {
+                    self.rb.ir.write(|w| unsafe {
+                        w.instruction().bits(instruction.bits())
+                    });
+                }
+
+                if address != XspiWord::None {
+                    // Write the address. The transaction starts on the next write
+                    // to DATA, unless there is no DATA phase configured, in which
+                    // case it starts here.
+                    self.rb.ar.write(|w| unsafe { w.address().bits(address.bits()) });
+                }
             }
 
             /// Begin a write over the XSPI interface. This is mostly useful for use with
@@ -596,33 +618,9 @@ mod common {
 
                 // Setup extended mode. Typically no dummy cycles in write mode
                 self.setup_extended(instruction, address, alternate_bytes, 0, !data.is_empty(), false);
-                // Write alternate-bytes
-                self.rb.abr.write(|w| unsafe {
-                    w.alternate().bits(alternate_bytes.bits())
-                });
-
-                if instruction != XspiWord::None {
-                    // Write instruction. If there is no address or data phase, the
-                    // transaction starts here.
-                    #[cfg(any(feature = "rm0433", feature = "rm0399"))]
-                    {
-                        let ir = instruction.bits_u8()?;
-                        self.rb.ccr.modify(|_, w| unsafe { w.instruction().bits(ir) });
-                    }
-                    #[cfg(any(feature = "rm0455", feature = "rm0468"))]
-                    self.rb.ir.write(|w| unsafe {
-                        w.instruction().bits(instruction.bits())
-                    });
-                }
-
-                if address != XspiWord::None {
-                    // Write the address. The transaction starts on the next write
-                    // to DATA, unless there is no DATA phase configured, in which
-                    // case it starts here.
-                    self.rb.ar.write(|w| unsafe { w.address().bits(address.bits()) });
-                }
 
                 // Write data to the FIFO in a byte-wise manner.
+                // Transaction starts here
                 unsafe {
                     for byte in data {
                         ptr::write_volatile(&self.rb.dr as *const _ as *mut u8, *byte);
@@ -765,37 +763,11 @@ mod common {
                     .dlr
                     .write(|w| unsafe { w.dl().bits(dest.len() as u32 - 1) });
 
-                // Setup extended mode. Read operations always have a data phase.  if there is no
-                // address, this will start the transaction
+                // Setup extended mode. Read operations always have a data phase.
+                // Transaction starts here
                 self.setup_extended(instruction, address, alternate_bytes,
                                     dummy_cycles, true, true);
 
-                // Write alternate-bytes
-                self.rb.abr.write(|w| unsafe {
-                    w.alternate().bits(alternate_bytes.bits())
-                });
-
-                /*
-                 * p894
-                 *
-                 * If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR)
-                 * need to be updated for a particular command, then the command sequence starts as
-                 * soon as QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are
-                 * 00, or if just ADMODE = 00 when in indirect read mode (FMODE = 01).
-                 *
-                 * When an address is required (ADMODE is not 00) and the data register does not
-                 * need to be written (when FMODE = 01 or DMODE = 00), the command sequence starts
-                 * as soon as the address is updated with a write to QUADSPI_AR.
-                 *
-                 * In case of data transmission (FMODE = 00 and DMODE! = 00), the communication
-                 * start is triggered by a write in the FIFO through QUADSPI_DR.
-                */
-
-                // Write the address if there is one, transaction starts here
-                if address != XspiWord::None {
-                    self.rb.ar.write(|w| unsafe { w.address().bits(address.bits()) });
-                }
-
                 // Wait for the transaction to complete
                 while self.rb.sr.read().tcf().bit_is_clear() {}