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Add OCTOSPI Hyperbus support and an example for HyperRAM usage
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-23
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4 files changed

+570
-23
lines changed

‎Cargo.toml

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@@ -159,6 +159,10 @@ required-features = ["xspi", "rm0433"]
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name = "octospi"
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required-features = ["xspi", "rm0468"]
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[[example]]
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name = "octospi_hyperram"
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required-features = ["xspi", "rm0468"]
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[[example]]
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name = "sdmmc"
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required-features = ["sdmmc", "rm0433"]

‎examples/octospi_hyperram.rs

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@@ -0,0 +1,172 @@
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//! Example using a OCTOSPI HyperRAM in memory-mapped mode
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//!
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//! Tested on a STM32H735G-DK with a Cypress S70KL1281DABHI023
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#![deny(warnings)]
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#![no_main]
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#![no_std]
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use core::mem;
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use core::slice;
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#[macro_use]
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mod utilities;
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use cortex_m_rt::entry;
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use stm32h7xx_hal::rcc::rec::{OctospiClkSel, OctospiClkSelGetter};
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use stm32h7xx_hal::{gpio::Speed::High, pac, prelude::*, xspi::HyperbusConfig};
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use log::info;
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#[entry]
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fn main() -> ! {
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utilities::logger::init();
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let dp = pac::Peripherals::take().unwrap();
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// Constrain and Freeze power
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let pwr = dp.PWR.constrain();
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let pwrcfg = example_power!(pwr).freeze();
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// Constrain and Freeze clock
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let rcc = dp.RCC.constrain();
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let ccdr = rcc.sys_ck(320.mhz()).freeze(pwrcfg, &dp.SYSCFG);
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// Octospi from HCLK at 160MHz
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assert_eq!(ccdr.clocks.hclk().0, 160_000_000);
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assert_eq!(
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ccdr.peripheral.OCTOSPI1.get_kernel_clk_mux(),
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OctospiClkSel::RCC_HCLK3
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);
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// Acquire the GPIO peripherals. This also enables the clock for
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// the GPIOs in the RCC register.
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let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
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let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
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let gpiof = dp.GPIOF.split(ccdr.peripheral.GPIOF);
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let _tracweswo = gpiob.pb3.into_alternate_af0();
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let _ncs = gpiog
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.pg12
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.into_alternate_af3()
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.set_speed(High)
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.internal_pull_up(true);
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let _dqs = gpiof
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.pf12
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _clk = gpiof
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.pf4
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io0 = gpiof
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.pf0
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io1 = gpiof
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.pf1
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io2 = gpiof
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.pf2
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io3 = gpiof
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.pf3
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io4 = gpiog
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.pg0
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io5 = gpiog
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.pg1
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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let _io6 = gpiog
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.pg10
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.into_alternate_af3()
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.set_speed(High)
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.internal_pull_up(true);
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let _io7 = gpiog
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.pg11
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.into_alternate_af9()
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.set_speed(High)
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.internal_pull_up(true);
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info!("");
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info!("stm32h7xx-hal example - OCTOSPI HyperRAM");
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info!("");
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// Initialise a HyperRAM on the OCTOSPI2 peripheral
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let ram_slice = unsafe {
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let hyperram_size = 16 * 1024 * 1024; // 16 MByte
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let config = HyperbusConfig::new(80.mhz())
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.device_size_bytes(24) // 16 Mbyte
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.refresh_interval(4.us())
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.read_write_recovery(4) // 50ns
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.access_initial_latency(6);
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let hyperram = dp.OCTOSPI2.octospi_hyperbus_unchecked(
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config,
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&ccdr.clocks,
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ccdr.peripheral.OCTOSPI2,
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);
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info!("Created HyperRAM..");
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info!("{}", hyperram);
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info!("");
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// Initialise and convert raw pointer to slice
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let ram_ptr: *mut u32 = hyperram.init();
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slice::from_raw_parts_mut(
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ram_ptr,
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hyperram_size / mem::size_of::<u32>(),
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)
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};
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info!("Writing checkerboard pattern...");
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for x in ram_slice.iter_mut() {
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*x = 0xAA55AA55;
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}
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info!("Reading checkerboard pattern...");
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for (i, x) in ram_slice.iter().enumerate() {
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assert_eq!(
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*x,
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0xAA55AA55,
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"Mismatch at address 0x{:x} (0x{:x} != 0xaa55aa55)",
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i * 4,
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*x
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);
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}
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info!("Writing reverse checkerboard pattern...");
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for x in ram_slice.iter_mut() {
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*x = 0x55AA55AA;
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}
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info!("Reading reverse checkerboard pattern...");
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for (i, x) in ram_slice.iter().enumerate() {
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assert_eq!(
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*x,
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0x55AA55AA,
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"Mismatch at address 0x{:x} (0x{:x} != 0x55aa55aa)",
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i * 4,
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*x
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);
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}
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info!("Success!");
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info!("");
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loop {
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cortex_m::asm::nop();
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}
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}

‎src/xspi/mod.rs

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Original file line numberDiff line numberDiff line change
@@ -62,6 +62,28 @@
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//! ```
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//! use stm32h7xx_hal::xspi;
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//! let config = xspi::Config::new(12.mhz()).fifo_threshold(16);
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//!
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//! # Hyperbus
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//!
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//! This driver supports a memory-mapped Hyperbus mode for the OCTOSPI
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//! peripheral.
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//!
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//! ```
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//! let config = HyperbusConfig::new(80.mhz())
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//! .device_size_bytes(24) // 16 Mbyte
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//! .refresh_interval(4.us())
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//! .read_write_recovery(4) // 50ns
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//! .access_initial_latency(6);
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//!
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//! let hyperram = dp.OCTOSPI1.octospi_hyperbus_unchecked(
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//! config,
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//! &ccdr.clocks,
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//! ccdr.peripheral.OCTOSPI1,
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//! );
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//!
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//! // Initialise and convert raw pointer to slice
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//! let ram_ptr: *mut u32 = hyperram.init();
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//! let ram = unsafe { slice::from_raw_parts_mut(ram_ptr, size_u32) };
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//! ```
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//!
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//! # Examples
@@ -74,7 +96,8 @@
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//! # Limitations
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//!
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//! This driver currently only supports indirect operation mode of the xSPI
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//! interface. Automatic polling or memory-mapped modes are not supported.
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//! interface. Automatic polling or memory-mapped modes are not supported,
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//! except for the OCTOSPI Hyperbus mode.
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//!
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//! Using different operational modes (1-bit/2-bit/4-bit etc.) for different
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//! phases of a single transaction is not supported. It is possible to change
@@ -106,7 +129,7 @@ pub use common::{
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XspiWord as OctospiWord,
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};
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#[cfg(any(feature = "rm0455", feature = "rm0468"))]
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pub use octospi::OctospiExt as XspiExt;
132+
pub use octospi::{Hyperbus, HyperbusConfig, OctospiExt as XspiExt};
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// Both
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pub use common::{Config, Event, SamplingEdge};
@@ -280,7 +303,7 @@ mod common {
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/// With zero dummy cycles, the QUADSPI peripheral will erroneously drive the
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/// output pins for an extra half clock cycle before IO is swapped from
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/// output to input. Refer to
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/// https://github.com/quartiq/stabilizer/issues/101 for more information.
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/// <https://github.com/quartiq/stabilizer/issues/101> for more information.
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pub fn dummy_cycles(mut self, cycles: u8) -> Self {
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debug_assert!(
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cycles < 32,
@@ -298,7 +321,7 @@ mod common {
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/// If zero dummy cycles are used, during read operations the QUADSPI
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/// peripheral will erroneously drive the output pins for an extra half
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/// clock cycle before IO is swapped from output to input. Refer to
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/// https://github.com/quartiq/stabilizer/issues/101 for more information.
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/// <https://github.com/quartiq/stabilizer/issues/101> for more information.
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///
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/// In this case it is recommended to sample on the falling edge. Although
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/// this doesn't stop the possible bus contention, delaying the sampling
@@ -461,22 +484,6 @@ mod common {
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.dmode() // data phase
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.bits(self.mode.reg_value())
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});
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465-
// if mode == XspiMode::EightBit {
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// // TODO
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// self.rb.ccr.modify(|_, w| unsafe {
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// w.admode()
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// .bits(mode.reg_value())
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// .adsize()
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// .bits(3) // 32-bit
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// .isize()
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// .bits(1) // 16-bit
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// .imode()
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// .bits(mode.reg_value())
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// .dmode()
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// .bits(mode.reg_value())
478-
// });
479-
// self.rb.tcr.write(|w| unsafe { w.dcyc().bits(4) });
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}
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482489
/// Sets the interface in extended mode

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