Merge #76

76: Add quadspi r=ryan-summers a=jordens

@ryan-summers I went ahead and drafted this PR to be able to discuss it.

Co-authored-by: Ryan Summers <[email protected]>
Co-authored-by: Robert Jördens <[email protected]>

Author: 3 people

.github/workflows/ci.yml

@@ -32,8 +32,8 @@ jobs:
         with:
           use-cross: true
           command: build
-          args: --verbose --release --examples --target thumbv7em-none-eabihf --features rt,${{ matrix.mcu }}
+          args: --verbose --release --examples --target thumbv7em-none-eabihf --features rt,quadspi,${{ matrix.mcu }}
       - uses: actions-rs/cargo@v1
         with:
           command: test
-          args: --lib --target x86_64-unknown-linux-gnu --features rt,${{ matrix.mcu }}
+          args: --lib --target x86_64-unknown-linux-gnu --features rt,${{ matrix.mcu }},quadspi

.github/workflows/nightly.yml

@@ -20,8 +20,8 @@ jobs:
         with:
           use-cross: true
           command: build
-          args: --verbose --release --examples --target thumbv7em-none-eabihf --features rt,stm32h743v
+          args: --verbose --release --examples --target thumbv7em-none-eabihf --features rt,stm32h743v,quadspi
       - uses: actions-rs/cargo@v1
         with:
           command: test
-          args: --lib --target x86_64-unknown-linux-gnu --features rt,stm32h743v
+          args: --lib --target x86_64-unknown-linux-gnu --features rt,stm32h743v,quadspi

Cargo.toml

@@ -50,6 +50,7 @@ dualcore = []
 dsi = []
 cm4 = []
 cm7 = []
+quadspi = []
 rt = ["stm32h7/rt"]
 stm32h742 = ["stm32h7/stm32h743", "device-selected", "singlecore"]
 stm32h743 = ["stm32h7/stm32h743", "device-selected", "singlecore"]
@@ -84,3 +85,7 @@ required-features = ["rt"]
 [[example]]
 name = "vos0"
 required-features = ["revision_v"]
+
+[[example]]
+name = "qspi"
+required-features = ["quadspi"]

examples/qspi.rs

@@ -0,0 +1,54 @@
+#![deny(warnings)]
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+
+extern crate panic_itm;
+
+use cortex_m_rt::entry;
+use stm32h7xx_hal::{pac, prelude::*, qspi::QspiMode};
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+
+    // Constrain and Freeze power
+    let pwr = dp.PWR.constrain();
+    let vos = pwr.freeze();
+
+    // Constrain and Freeze clock
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(96.mhz()).freeze(vos, &dp.SYSCFG);
+
+    // Acquire the GPIO peripherals. This also enables the clock for
+    // the GPIOs in the RCC register.
+    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
+    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
+    let gpiod = dp.GPIOD.split(ccdr.peripheral.GPIOD);
+    let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+
+    let _qspi_cs = gpiog.pg6.into_alternate_af10();
+
+    let sck = gpiob.pb2.into_alternate_af9();
+    let io0 = gpiod.pd11.into_alternate_af9();
+    let io1 = gpiod.pd12.into_alternate_af9();
+    let io2 = gpioe.pe2.into_alternate_af9();
+    let io3 = gpiod.pd13.into_alternate_af9();
+
+    // Initialise the QSPI peripheral.
+    let mut qspi = dp.QUADSPI.bank1(
+        (sck, io0, io1, io2, io3),
+        3.mhz(),
+        &ccdr.clocks,
+        ccdr.peripheral.QSPI,
+    );
+
+    qspi.configure_mode(QspiMode::FourBit).unwrap();
+
+    loop {
+        qspi.write(0x00, &[0xAA, 0x00, 0xFF]).unwrap();
+
+        let mut read: [u8; 3] = [0; 3];
+        qspi.read(0xFF, &mut read).unwrap();
+    }
+}

src/lib.rs

@@ -129,6 +129,8 @@ pub mod pwm;
 pub mod pwr;
 #[cfg(feature = "device-selected")]
 pub mod qei;
+#[cfg(all(feature = "device-selected", feature = "quadspi"))]
+pub mod qspi;
 #[cfg(feature = "device-selected")]
 pub mod rcc;
 #[cfg(feature = "device-selected")]

src/prelude.rs

@@ -10,6 +10,8 @@ pub use crate::gpio::GpioExt as _stm32h7xx_hal_gpio_GpioExt;
 pub use crate::i2c::I2cExt as _stm32h7xx_hal_i2c_I2cExt;
 pub use crate::pwm::PwmExt as _stm32_hal_pwm_PwmExt;
 pub use crate::pwr::PwrExt as _stm32h7xx_hal_pwr_PwrExt;
+#[cfg(feature = "quadspi")]
+pub use crate::qspi::QspiExt as _stm32h7xx_hal_qspi_QspiExt;
 pub use crate::rcc::RccExt as _stm32h7xx_hal_rcc_RccExt;
 pub use crate::rng::RngCore as _stm32h7xx_hal_rng_RngCore;
 pub use crate::rng::RngExt as _stm32h7xx_hal_rng_RngExt;