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Update for new pac
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-1530
lines changed

‎Cargo.toml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,8 @@ embedded-hal = { version = "0.2.6", features = ["unproven"] }
3232
embedded-dma = "0.2.0"
3333
cortex-m = { version = "^0.7.7", features = ["critical-section-single-core"] }
3434
defmt = { version = ">=0.2.0,<0.4", optional = true }
35-
stm32h7 = { version = "^0.15.1", default-features = false }
35+
#stm32h7 = { version = "^0.15.1", default-features = false }
36+
stm32h7 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", default-features = false }
3637
void = { version = "1.0.2", default-features = false }
3738
cast = { version = "0.3.0", default-features = false }
3839
nb = "1.0.0"

‎src/adc.rs

Lines changed: 89 additions & 81 deletions
Large diffs are not rendered by default.

‎src/can.rs

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -94,15 +94,15 @@ macro_rules! message_ram_layout {
9494
let mut word_adr: u16 = $start_word_addr;
9595

9696
// 11-bit filter
97-
$can.sidfc
97+
$can.sidfc()
9898
.modify(|_, w| unsafe { w.flssa().bits(word_adr) });
9999
word_adr += STANDARD_FILTER_MAX as u16;
100100
// 29-bit filter
101-
$can.xidfc
101+
$can.xidfc()
102102
.modify(|_, w| unsafe { w.flesa().bits(word_adr) });
103103
word_adr += 2 * EXTENDED_FILTER_MAX as u16;
104104
// Rx FIFO 0
105-
$can.rxf0c.modify(|_, w| unsafe {
105+
$can.rxf0c().modify(|_, w| unsafe {
106106
w.f0sa()
107107
.bits(word_adr)
108108
.f0s()
@@ -112,7 +112,7 @@ macro_rules! message_ram_layout {
112112
});
113113
word_adr += 18 * RX_FIFO_MAX as u16;
114114
// Rx FIFO 1
115-
$can.rxf1c.modify(|_, w| unsafe {
115+
$can.rxf1c().modify(|_, w| unsafe {
116116
w.f1sa()
117117
.bits(word_adr)
118118
.f1s()
@@ -123,7 +123,7 @@ macro_rules! message_ram_layout {
123123
word_adr += 18 * RX_FIFO_MAX as u16;
124124
// Rx buffer - see below
125125
// Tx event FIFO
126-
$can.txefc.modify(|_, w| unsafe {
126+
$can.txefc().modify(|_, w| unsafe {
127127
w.efsa()
128128
.bits(word_adr)
129129
.efs()
@@ -133,22 +133,23 @@ macro_rules! message_ram_layout {
133133
});
134134
word_adr += 2 * TX_EVENT_MAX as u16;
135135
// Tx buffers
136-
$can.txbc.modify(|_, w| unsafe {
136+
$can.txbc().modify(|_, w| unsafe {
137137
w.tbsa().bits(word_adr).tfqs().bits(TX_FIFO_MAX)
138138
});
139139
word_adr += 18 * TX_FIFO_MAX as u16;
140140

141141
// Rx Buffer - not used
142-
$can.rxbc.modify(|_, w| unsafe { w.rbsa().bits(word_adr) });
142+
$can.rxbc()
143+
.modify(|_, w| unsafe { w.rbsa().bits(word_adr) });
143144

144145
// TX event FIFO?
145146
// Trigger memory?
146147

147148
// Set the element sizes to 16 bytes
148-
$can.rxesc.modify(|_, w| unsafe {
149+
$can.rxesc().modify(|_, w| unsafe {
149150
w.rbds().bits(0b111).f1ds().bits(0b111).f0ds().bits(0b111)
150151
});
151-
$can.txesc.modify(|_, w| unsafe { w.tbds().bits(0b111) });
152+
$can.txesc().modify(|_, w| unsafe { w.tbds().bits(0b111) });
152153
};
153154
}
154155

‎src/crc.rs

Lines changed: 31 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@ impl Crc {
3737

3838
// manual says unit must be reset (or DR read) before change of polynomial
3939
// (technically only in case of ongoing calculation, but DR is buffered)
40-
self.reg.cr.modify(|_, w| {
40+
//NOTE(unsafe) Only valid bit patterns are written
41+
self.reg.cr().modify(|_, w| unsafe {
4142
w.polysize()
4243
.bits(config.poly.polysize())
4344
.rev_in()
@@ -47,8 +48,14 @@ impl Crc {
4748
.reset()
4849
.set_bit()
4950
});
50-
self.reg.pol.write(|w| w.pol().bits(config.poly.pol()));
51-
self.reg.init.write(|w| w.init().bits(config.initial));
51+
//NOTE(unsafe) All bit patterns are valid
52+
self.reg
53+
.pol()
54+
.write(|w| unsafe { w.pol().bits(config.poly.pol()) });
55+
//NOTE(unsafe) All bit patterns are valid
56+
self.reg
57+
.init()
58+
.write(|w| unsafe { w.init().bits(config.initial) });
5259
// writing to INIT sets DR to its value
5360
}
5461

@@ -60,18 +67,23 @@ impl Crc {
6067
let mut words = data.chunks_exact(4);
6168
for word in words.by_ref() {
6269
let word = u32::from_be_bytes(word.try_into().unwrap());
63-
self.reg.dr().write(|w| w.dr().bits(word));
70+
//NOTE(unsafe) All bit patterns are valid
71+
self.reg.dr().write(|w| unsafe { w.dr().bits(word) });
6472
}
6573

6674
// there will be at most 3 bytes remaining, so 1 half-word and 1 byte
6775
let mut half_word = words.remainder().chunks_exact(2);
6876
if let Some(half_word) = half_word.next() {
6977
let half_word = u16::from_be_bytes(half_word.try_into().unwrap());
70-
self.reg.dr16().write(|w| w.dr16().bits(half_word));
78+
//NOTE(unsafe) All bit patterns are valid
79+
self.reg
80+
.dr16()
81+
.write(|w| unsafe { w.dr16().bits(half_word) });
7182
}
7283

7384
if let Some(byte) = half_word.remainder().first() {
74-
self.reg.dr8().write(|w| w.dr8().bits(*byte));
85+
//NOTE(unsafe) All bit patterns are valid
86+
self.reg.dr8().write(|w| unsafe { w.dr8().bits(*byte) });
7587
}
7688
}
7789

@@ -87,7 +99,7 @@ impl Crc {
8799
/// This does not reset the configuration options.
88100
pub fn finish(&mut self) -> u32 {
89101
let result = self.read_crc();
90-
self.reg.cr.modify(|_, w| w.reset().set_bit());
102+
self.reg.cr().modify(|_, w| w.reset().set_bit());
91103
result
92104
}
93105

@@ -105,7 +117,7 @@ impl Crc {
105117
/// algorithm that does not apply an output XOR or reverse the output bits.
106118
pub fn read_state(&self) -> u32 {
107119
let state = self.read_crc_no_xor();
108-
if self.reg.cr.read().rev_out().is_reversed() {
120+
if self.reg.cr().read().rev_out().is_reversed() {
109121
state.reverse_bits()
110122
} else {
111123
state
@@ -123,14 +135,15 @@ impl Crc {
123135
///
124136
/// The IDR is not involved with CRC calculation.
125137
pub fn set_idr(&mut self, value: u32) {
126-
self.reg.idr.write(|w| w.idr().bits(value));
138+
//NOTE(unsafe) All bit patterns are valid
139+
self.reg.idr().write(|w| unsafe { w.idr().bits(value) });
127140
}
128141

129142
/// Get the current value of the independent data register.
130143
///
131144
/// The IDR is not involved with CRC calculation.
132145
pub fn get_idr(&self) -> u32 {
133-
self.reg.idr.read().idr().bits()
146+
self.reg.idr().read().idr().bits()
134147
}
135148

136149
/// Returns a reference to the inner peripheral
@@ -226,10 +239,10 @@ impl Polynomial {
226239
/// Return POLYSIZE register value.
227240
const fn polysize(self) -> u8 {
228241
(match self.0 {
229-
Poly::B7(_) => crc::cr::POLYSIZE_A::Polysize7,
230-
Poly::B8(_) => crc::cr::POLYSIZE_A::Polysize8,
231-
Poly::B16(_) => crc::cr::POLYSIZE_A::Polysize16,
232-
Poly::B32(_) => crc::cr::POLYSIZE_A::Polysize32,
242+
Poly::B7(_) => crc::cr::POLYSIZE::Polysize7,
243+
Poly::B8(_) => crc::cr::POLYSIZE::Polysize8,
244+
Poly::B16(_) => crc::cr::POLYSIZE::Polysize16,
245+
Poly::B32(_) => crc::cr::POLYSIZE::Polysize32,
233246
}) as u8
234247
}
235248

@@ -307,11 +320,11 @@ enum Poly {
307320
#[repr(u8)]
308321
pub enum BitReversal {
309322
/// Each input byte has its bits reversed. `0x1A2B3C4D` becomes `0x58D43CB2`.
310-
Byte = crc::cr::REV_IN_A::Byte as u8,
323+
Byte = crc::cr::REV_IN::Byte as u8,
311324
/// Bits reversed by half-word. `0x1A2B3C4D` becomes `0xD458B23C`.
312-
HalfWord = crc::cr::REV_IN_A::HalfWord as u8,
325+
HalfWord = crc::cr::REV_IN::HalfWord as u8,
313326
/// Bits reversed by word. `0x1A2B3C4D` becomes `0xB23CD458`.
314-
Word = crc::cr::REV_IN_A::Word as u8,
327+
Word = crc::cr::REV_IN::Word as u8,
315328
}
316329

317330
/// CRC unit configuration.
@@ -368,7 +381,7 @@ impl Config {
368381
fn get_reverse_input(&self) -> u8 {
369382
self.reverse_input
370383
.map(|rev| rev as u8)
371-
.unwrap_or(crc::cr::REV_IN_A::Normal as u8)
384+
.unwrap_or(crc::cr::REV_IN::Normal as u8)
372385
}
373386

374387
/// Set whether to reverse the bits of the output.

‎src/dac.rs

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -88,8 +88,8 @@ macro_rules! dac {
8888
pub fn enable(self) -> $CX<$DAC, Enabled> {
8989
let dac = unsafe { &(*$DAC::ptr()) };
9090

91-
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
92-
dac.cr.modify(|_, w| w.$en().set_bit());
91+
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
92+
dac.cr().modify(|_, w| w.$en().set_bit());
9393

9494
$CX {
9595
_dac: PhantomData,
@@ -100,8 +100,8 @@ macro_rules! dac {
100100
pub fn enable_unbuffered(self) -> $CX<$DAC, EnabledUnbuffered> {
101101
let dac = unsafe { &(*$DAC::ptr()) };
102102

103-
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
104-
dac.cr.modify(|_, w| w.$en().set_bit());
103+
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(2) });
104+
dac.cr().modify(|_, w| w.$en().set_bit());
105105

106106
$CX {
107107
_dac: PhantomData,
@@ -130,19 +130,19 @@ macro_rules! dac {
130130
T: DelayUs<u32>,
131131
{
132132
let dac = unsafe { &(*$DAC::ptr()) };
133-
dac.cr.modify(|_, w| w.$en().clear_bit());
134-
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
135-
dac.cr.modify(|_, w| w.$cen().set_bit());
133+
dac.cr().modify(|_, w| w.$en().clear_bit());
134+
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
135+
dac.cr().modify(|_, w| w.$cen().set_bit());
136136
let mut trim = 0;
137137
while true {
138-
dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
138+
dac.ccr().modify(|_, w| unsafe { w.$trim().bits(trim) });
139139
delay.delay_us(64_u32);
140-
if dac.sr.read().$cal_flag().bit() {
140+
if dac.sr().read().$cal_flag().bit() {
141141
break;
142142
}
143143
trim += 1;
144144
}
145-
dac.cr.modify(|_, w| w.$cen().clear_bit());
145+
dac.cr().modify(|_, w| w.$cen().clear_bit());
146146

147147
$CX {
148148
_dac: PhantomData,
@@ -153,7 +153,7 @@ macro_rules! dac {
153153
/// Disable the DAC channel
154154
pub fn disable(self) -> $CX<$DAC, Disabled> {
155155
let dac = unsafe { &(*$DAC::ptr()) };
156-
dac.cr.modify(|_, w| w.$en().clear_bit());
156+
dac.cr().modify(|_, w| w.$en().clear_bit());
157157

158158
$CX {
159159
_dac: PhantomData,
@@ -166,12 +166,12 @@ macro_rules! dac {
166166
impl<ED> DacOut<u16> for $CX<$DAC, ED> {
167167
fn set_value(&mut self, val: u16) {
168168
let dac = unsafe { &(*$DAC::ptr()) };
169-
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
169+
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
170170
}
171171

172172
fn get_value(&mut self) -> u16 {
173173
let dac = unsafe { &(*$DAC::ptr()) };
174-
dac.$dor.read().bits() as u16
174+
dac.$dor().read().bits() as u16
175175
}
176176
}
177177
};

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