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Set synchronous bits on USART peripheral only, for others they are reserved
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-31
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1 file changed

+48
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src/serial.rs

Lines changed: 48 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -440,9 +440,14 @@ pub trait SerialExt<USART>: Sized {
440440
}
441441
}
442442

443+
macro_rules! replace_expr {
444+
($_t:tt $sub:expr) => {
445+
$sub
446+
};
447+
}
443448
macro_rules! usart {
444449
($(
445-
$USARTX:ident: ($usartX:ident, $Rec:ident, $pclkX:ident),
450+
$USARTX:ident: ($usartX:ident, $Rec:ident, $pclkX:ident $(, $synchronous:ident)?),
446451
)+) => {
447452
$(
448453
/// Configures a USART peripheral to provide serial
@@ -452,8 +457,8 @@ macro_rules! usart {
452457
usart: $USARTX,
453458
config: impl Into<config::Config>,
454459
prec: rec::$Rec,
455-
clocks: &CoreClocks,
456-
synchronous: bool
460+
clocks: &CoreClocks
461+
$(, $synchronous: bool)?
457462
) -> Result<Self, config::InvalidConfig>
458463
{
459464
use crate::stm32::usart1::cr2::STOP_A as STOP;
@@ -504,28 +509,33 @@ macro_rules! usart {
504509
BitOrder::MsbFirst => MSBFIRST_A::MSB,
505510
});
506511

507-
w.lbcl().variant(if config.lastbitclockpulse {
508-
LBCL_A::OUTPUT
509-
} else {
510-
LBCL_A::NOTOUTPUT
511-
});
512-
513-
w.clken().variant(if synchronous {
514-
CLKEN_A::ENABLED
515-
} else {
516-
CLKEN_A::DISABLED
517-
});
518-
519-
w.cpol().variant(match config.clockpolarity {
520-
ClockPolarity::IdleHigh =>CPOL_A::HIGH,
521-
ClockPolarity::IdleLow =>CPOL_A::LOW
522-
});
523-
524-
w.cpha().variant(match config.clockphase {
525-
ClockPhase::First => CPHA_A::FIRST,
526-
ClockPhase::Second => CPHA_A::SECOND
527-
})
528-
512+
// If synchronous mode is not supported, these bits are
513+
// reserved and must be kept at reset value
514+
$(
515+
w.lbcl().variant(if config.lastbitclockpulse {
516+
LBCL_A::OUTPUT
517+
} else {
518+
LBCL_A::NOTOUTPUT
519+
});
520+
521+
w.clken().variant(if $synchronous {
522+
CLKEN_A::ENABLED
523+
} else {
524+
CLKEN_A::DISABLED
525+
});
526+
527+
w.cpol().variant(match config.clockpolarity {
528+
ClockPolarity::IdleHigh =>CPOL_A::HIGH,
529+
ClockPolarity::IdleLow =>CPOL_A::LOW
530+
});
531+
532+
w.cpha().variant(match config.clockphase {
533+
ClockPhase::First => CPHA_A::FIRST,
534+
ClockPhase::Second => CPHA_A::SECOND
535+
});
536+
)?
537+
538+
w
529539
});
530540

531541
// Enable transmission and receiving
@@ -675,17 +685,24 @@ macro_rules! usart {
675685
clocks: &CoreClocks
676686
) -> Result<Serial<$USARTX>, config::InvalidConfig>
677687
{
678-
Serial::$usartX(self, config, prec, clocks, P::SYNCHRONOUS)
688+
Serial::$usartX(
689+
self, config, prec, clocks
690+
$(, replace_expr!($synchronous P::SYNCHRONOUS))?
691+
)
679692
}
680693

681694
fn serial_unchecked(self,
682695
config: impl Into<config::Config>,
683696
prec: rec::$Rec,
684697
clocks: &CoreClocks,
698+
#[allow(unused)]
685699
synchronous: bool,
686700
) -> Result<Serial<$USARTX>, config::InvalidConfig>
687701
{
688-
Serial::$usartX(self, config, prec, clocks, synchronous)
702+
Serial::$usartX(
703+
self, config, prec, clocks
704+
$(, replace_expr!($synchronous synchronous))?
705+
)
689706
}
690707
}
691708

@@ -913,10 +930,10 @@ macro_rules! usart_sel {
913930
}
914931

915932
usart! {
916-
USART1: (usart1, Usart1, pclk2),
917-
USART2: (usart2, Usart2, pclk1),
918-
USART3: (usart3, Usart3, pclk1),
919-
USART6: (usart6, Usart6, pclk2),
933+
USART1: (usart1, Usart1, pclk2, synchronous),
934+
USART2: (usart2, Usart2, pclk1, synchronous),
935+
USART3: (usart3, Usart3, pclk1, synchronous),
936+
USART6: (usart6, Usart6, pclk2, synchronous),
920937

921938
UART4: (uart4, Uart4, pclk1),
922939
UART5: (uart5, Uart5, pclk1),

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