Disable ethernet MAC MMC counter interrupts

Patch from quartiq/stabilizer#462

Tested that the expected registers are indeed set on a STM32H747I-DISCO

> MMC_RX_INTERRUPT_MASK:               0x0C020060  MMC Rx interrupt mask register
> MMC_TX_INTERRUPT_MASK:               0x0C20C000  MMC Tx interrupt mask register

Closes #275

Author: richardeoin

src/ethernet/eth.rs

@@ -428,6 +428,12 @@ pub fn new<'a, const TD: usize, const RD: usize>(
 /// [StationManagement](super::StationManagement) trait. This can be used to
 /// communicate with the external PHY.
 ///
+/// All the documented interrupts in the `MMC_TX_INTERRUPT_MASK` and
+/// `MMC_RX_INTERRUPT_MASK` registers are masked, since these cause unexpected
+/// interrupts after a number of days of heavy ethernet traffic. If these
+/// interrupts are desired, you can be unmask them in your own code after this
+/// method.
+///
 /// # Safety
 ///
 /// `EthernetDMA` shall not be moved as it is initialised here
@@ -572,6 +578,46 @@ pub unsafe fn new_unchecked<'a, const TD: usize, const RD: usize>(
             w.pt().bits(0x100)
         });
         eth_mac.macrx_fcr.modify(|_, w| w);
+
+        // Mask away Ethernet MAC MMC RX/TX interrupts. These are statistics
+        // counter interrupts and are enabled by default. We need to manually
+        // disable various ethernet interrupts so they don't unintentionally
+        // hang the device. The user is free to re-enable them later to provide
+        // ethernet MAC-related statistics
+        eth_mac.mmc_rx_interrupt_mask.modify(|_, w| {
+            w.rxlpiuscim()
+                .set_bit()
+                .rxucgpim()
+                .set_bit()
+                .rxalgnerpim()
+                .set_bit()
+                .rxcrcerpim()
+                .set_bit()
+        });
+
+        eth_mac.mmc_tx_interrupt_mask.modify(|_, w| {
+            w.txlpiuscim()
+                .set_bit()
+                .txgpktim()
+                .set_bit()
+                .txmcolgpim()
+                .set_bit()
+                .txscolgpim()
+                .set_bit()
+        });
+        // TODO: The MMC_TX/RX_INTERRUPT_MASK registers incorrectly mark
+        // LPITRCIM as read-only, so svd2rust doens't generate bindings to
+        // modify them. Instead, as a workaround, we manually manipulate the
+        // bits
+        unsafe {
+            eth_mac
+                .mmc_tx_interrupt_mask
+                .modify(|r, w| w.bits(r.bits() | (1 << 27)));
+            eth_mac
+                .mmc_rx_interrupt_mask
+                .modify(|r, w| w.bits(r.bits() | (1 << 27)));
+        }
+
         eth_mtl.mtlrx_qomr.modify(|_, w| {
             w
                 // Receive store and forward