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qspi
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-207
lines changed

2 files changed

+85
-207
lines changed

‎src/gpio/alt.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1773,16 +1773,16 @@ pub mod quadspi {
17731773
PD11<9>,
17741774
PF8<10>,
17751775
],
1776-
<Bk1Io1> for [
1776+
<Bk1Io1> for no:NoPin, [
17771777
PC10<9>,
17781778
PD12<9>,
17791779
PF9<10>,
17801780
],
1781-
<Bk1Io2> for [
1781+
<Bk1Io2> for no:NoPin, [
17821782
PE2<9>,
17831783
PF7<9>,
17841784
],
1785-
<Bk1Io3> for [
1785+
<Bk1Io3> for no:NoPin, [
17861786
PA1<9>,
17871787
PD13<9>,
17881788
PF6<9>,
@@ -1796,15 +1796,15 @@ pub mod quadspi {
17961796
PE7<10>,
17971797
PH2<9>,
17981798
],
1799-
<Bk2Io1> for [
1799+
<Bk2Io1> for no:NoPin, [
18001800
PE8<10>,
18011801
PH3<9>,
18021802
],
1803-
<Bk2Io2> for [
1803+
<Bk2Io2> for no:NoPin, [
18041804
PE9<10>,
18051805
PG9<9>,
18061806
],
1807-
<Bk2Io3> for [
1807+
<Bk2Io3> for no:NoPin, [
18081808
PE10<10>,
18091809
PG14<9>,
18101810
],

‎src/xspi/qspi.rs

Lines changed: 79 additions & 201 deletions
Original file line numberDiff line numberDiff line change
@@ -3,183 +3,104 @@
33
//! See the parent module for documentation
44
55
use crate::{
6-
gpio::{self, Alternate},
6+
gpio::{self, alt::quadspi as alt, Alternate},
77
rcc::{rec, CoreClocks, ResetEnable},
88
stm32,
99
};
1010

1111
use super::{Bank, Config, Qspi, SamplingEdge};
1212

1313
/// Used to indicate that an IO pin is not used by the QSPI interface.
14-
pub struct NoIo {}
14+
pub use gpio::NoPin as NoIo;
1515

1616
/// Indicates a set of pins can be used for the QSPI interface on bank 1.
17-
pub trait PinsBank1 {}
18-
pub trait PinIo0Bank1 {}
19-
pub trait PinIo1Bank1 {}
20-
pub trait PinIo2Bank1 {}
21-
pub trait PinIo3Bank1 {}
17+
pub trait PinsBank1 {
18+
type AltPins;
19+
fn convert(self) -> Self::AltPins;
20+
}
2221

2322
/// Indicates a set of pins can be used for the QSPI interface on bank 2.
24-
pub trait PinsBank2 {}
25-
pub trait PinSckBank2 {}
26-
pub trait PinIo0Bank2 {}
27-
pub trait PinIo1Bank2 {}
28-
pub trait PinIo2Bank2 {}
29-
pub trait PinIo3Bank2 {}
30-
31-
pub trait PinSck {}
23+
pub trait PinsBank2 {
24+
type AltPins;
25+
fn convert(self) -> Self::AltPins;
26+
}
3227

3328
impl<SCK, IO0, IO1, IO2, IO3> PinsBank1 for (SCK, IO0, IO1, IO2, IO3)
3429
where
35-
SCK: PinSck,
36-
IO0: PinIo0Bank1,
37-
IO1: PinIo1Bank1,
38-
IO2: PinIo2Bank1,
39-
IO3: PinIo3Bank1,
30+
SCK: Into<alt::Clk>,
31+
IO0: Into<alt::Bk1Io0>,
32+
IO1: Into<alt::Bk1Io1>,
33+
IO2: Into<alt::Bk1Io2>,
34+
IO3: Into<alt::Bk1Io3>,
4035
{
36+
type AltPins =
37+
(alt::Clk, alt::Bk1Io0, alt::Bk1Io1, alt::Bk1Io2, alt::Bk1Io3);
38+
fn convert(self) -> Self::AltPins {
39+
(
40+
self.0.into(),
41+
self.1.into(),
42+
self.2.into(),
43+
self.3.into(),
44+
self.4.into(),
45+
)
46+
}
4147
}
4248

4349
impl<SCK, IO0, IO1, IO2, IO3> PinsBank2 for (SCK, IO0, IO1, IO2, IO3)
4450
where
45-
SCK: PinSck,
46-
IO0: PinIo0Bank2,
47-
IO1: PinIo1Bank2,
48-
IO2: PinIo2Bank2,
49-
IO3: PinIo3Bank2,
51+
SCK: Into<alt::Clk>,
52+
IO0: Into<alt::Bk2Io0>,
53+
IO1: Into<alt::Bk2Io1>,
54+
IO2: Into<alt::Bk2Io2>,
55+
IO3: Into<alt::Bk2Io3>,
5056
{
57+
type AltPins =
58+
(alt::Clk, alt::Bk2Io0, alt::Bk2Io1, alt::Bk2Io2, alt::Bk2Io3);
59+
fn convert(self) -> Self::AltPins {
60+
(
61+
self.0.into(),
62+
self.1.into(),
63+
self.2.into(),
64+
self.3.into(),
65+
self.4.into(),
66+
)
67+
}
5168
}
5269

53-
macro_rules! pins {
54-
(Bank1: [IO0: [$($IO0:ty),*] IO1: [$($IO1:ty),*] IO2: [$($IO2:ty),*] IO3: [$($IO3:ty),*]]) => {
55-
$(
56-
impl PinIo0Bank1 for $IO0 {}
57-
)*
58-
$(
59-
impl PinIo1Bank1 for $IO1 {}
60-
)*
61-
$(
62-
impl PinIo2Bank1 for $IO2 {}
63-
)*
64-
$(
65-
impl PinIo3Bank1 for $IO3 {}
66-
)*
67-
};
68-
69-
(Bank2: [IO0: [$($IO0:ty),*] IO1: [$($IO1:ty),*] IO2: [$($IO2:ty),*] IO3: [$($IO3:ty),*]]) => {
70-
$(
71-
impl PinIo0Bank2 for $IO0 {}
72-
)*
73-
$(
74-
impl PinIo1Bank2 for $IO1 {}
75-
)*
76-
$(
77-
impl PinIo2Bank2 for $IO2 {}
78-
)*
79-
$(
80-
impl PinIo3Bank2 for $IO3 {}
81-
)*
82-
};
83-
84-
(SCK: [$($SCK:ty),*], Bank1: $bank1:tt, Bank2: $bank2:tt) => {
85-
$(
86-
impl PinSck for $SCK {}
87-
)*
88-
pins!(Bank1: $bank1);
89-
pins!(Bank2: $bank2);
90-
};
91-
}
92-
93-
pins! {
94-
SCK: [
95-
gpio::PB2<Alternate<9>>,
96-
gpio::PF10<Alternate<9>>
97-
],
98-
Bank1: [
99-
IO0: [
100-
gpio::PC9<Alternate<9>>,
101-
gpio::PD11<Alternate<9>>,
102-
gpio::PF8<Alternate<10>>
103-
]
104-
IO1: [
105-
gpio::PC10<Alternate<9>>,
106-
gpio::PD12<Alternate<9>>,
107-
gpio::PF9<Alternate<10>>,
108-
NoIo
109-
]
110-
IO2: [
111-
gpio::PE2<Alternate<9>>,
112-
gpio::PF7<Alternate<9>>,
113-
NoIo
114-
]
115-
IO3: [
116-
gpio::PA1<Alternate<9>>,
117-
gpio::PD13<Alternate<9>>,
118-
gpio::PF6<Alternate<9>>,
119-
NoIo
120-
]
121-
],
122-
Bank2: [
123-
IO0: [
124-
gpio::PE7<Alternate<10>>,
125-
gpio::PF8<Alternate<10>>,
126-
gpio::PH2<Alternate<9>>
127-
]
128-
IO1: [
129-
gpio::PE8<Alternate<10>>,
130-
gpio::PF9<Alternate<10>>,
131-
gpio::PH3<Alternate<9>>,
132-
NoIo
133-
]
134-
IO2: [
135-
gpio::PE9<Alternate<10>>,
136-
gpio::PG9<Alternate<9>>,
137-
NoIo
138-
]
139-
IO3: [
140-
gpio::PE10<Alternate<10>>,
141-
gpio::PG14<Alternate<9>>,
142-
NoIo
143-
]
144-
]
145-
}
146-
147-
pub trait QspiExt {
148-
fn bank1<CONFIG, PINS>(
70+
pub trait QspiExt: Sized {
71+
fn bank1(
14972
self,
150-
_pins: PINS,
151-
config: CONFIG,
73+
pins: impl PinsBank1,
74+
config: impl Into<Config>,
15275
clocks: &CoreClocks,
15376
prec: rec::Qspi,
154-
) -> Qspi<stm32::QUADSPI>
155-
where
156-
CONFIG: Into<Config>,
157-
PINS: PinsBank1;
77+
) -> Qspi<stm32::QUADSPI> {
78+
let _pins = pins.convert();
79+
Self::qspi_unchecked(self, config, Bank::One, clocks, prec)
80+
}
15881

159-
fn bank2<CONFIG, PINS>(
82+
fn bank2(
16083
self,
161-
_pins: PINS,
162-
config: CONFIG,
84+
pins: impl PinsBank2,
85+
config: impl Into<Config>,
16386
clocks: &CoreClocks,
16487
prec: rec::Qspi,
165-
) -> Qspi<stm32::QUADSPI>
166-
where
167-
CONFIG: Into<Config>,
168-
PINS: PinsBank2;
88+
) -> Qspi<stm32::QUADSPI> {
89+
let _pins = pins.convert();
90+
Self::qspi_unchecked(self, config, Bank::Two, clocks, prec)
91+
}
16992

170-
fn qspi_unchecked<CONFIG>(
93+
fn qspi_unchecked(
17194
self,
172-
config: CONFIG,
95+
config: impl Into<Config>,
17396
bank: Bank,
17497
clocks: &CoreClocks,
17598
prec: rec::Qspi,
176-
) -> Qspi<stm32::QUADSPI>
177-
where
178-
CONFIG: Into<Config>;
99+
) -> Qspi<stm32::QUADSPI>;
179100
}
180101

181102
impl Qspi<stm32::QUADSPI> {
182-
pub fn qspi_unchecked<CONFIG>(
103+
pub fn new_unchecked<CONFIG>(
183104
regs: stm32::QUADSPI,
184105
config: CONFIG,
185106
bank: Bank,
@@ -206,30 +127,20 @@ impl Qspi<stm32::QUADSPI> {
206127

207128
// Clear all pending flags.
208129
regs.fcr.write(|w| {
209-
w.ctof()
210-
.set_bit()
211-
.csmf()
212-
.set_bit()
213-
.ctcf()
214-
.set_bit()
215-
.ctef()
216-
.set_bit()
130+
w.ctof().set_bit();
131+
w.csmf().set_bit();
132+
w.ctcf().set_bit();
133+
w.ctef().set_bit()
217134
});
218135

219136
// Configure the communication method for QSPI.
220137
regs.ccr.write(|w| unsafe {
221-
w.fmode()
222-
.bits(0) // indirect mode
223-
.dmode()
224-
.bits(config.mode.reg_value())
225-
.admode()
226-
.bits(config.mode.reg_value())
227-
.adsize()
228-
.bits(0) // Eight-bit address
229-
.imode()
230-
.bits(0) // No instruction phase
231-
.dcyc()
232-
.bits(config.dummy_cycles)
138+
w.fmode().bits(0); // indirect mode
139+
w.dmode().bits(config.mode.reg_value());
140+
w.admode().bits(config.mode.reg_value());
141+
w.adsize().bits(0); // Eight-bit address
142+
w.imode().bits(0); // No instruction phase
143+
w.dcyc().bits(config.dummy_cycles)
233144
});
234145

235146
let spi_frequency = config.frequency.raw();
@@ -250,12 +161,10 @@ impl Qspi<stm32::QUADSPI> {
250161
//
251162
// SSHIFT must not be set in DDR mode.
252163
regs.cr.write(|w| unsafe {
253-
w.prescaler()
254-
.bits(divisor as u8)
255-
.sshift()
256-
.bit(config.sampling_edge == SamplingEdge::Falling)
257-
.fthres()
258-
.bits(config.fifo_threshold - 1)
164+
w.prescaler().bits(divisor as u8);
165+
w.sshift()
166+
.bit(config.sampling_edge == SamplingEdge::Falling);
167+
w.fthres().bits(config.fifo_threshold - 1)
259168
});
260169

261170
match bank {
@@ -275,44 +184,13 @@ impl Qspi<stm32::QUADSPI> {
275184
}
276185

277186
impl QspiExt for stm32::QUADSPI {
278-
fn bank1<CONFIG, PINS>(
187+
fn qspi_unchecked(
279188
self,
280-
_pins: PINS,
281-
config: CONFIG,
282-
clocks: &CoreClocks,
283-
prec: rec::Qspi,
284-
) -> Qspi<stm32::QUADSPI>
285-
where
286-
CONFIG: Into<Config>,
287-
PINS: PinsBank1,
288-
{
289-
Qspi::qspi_unchecked(self, config, Bank::One, clocks, prec)
290-
}
291-
292-
fn bank2<CONFIG, PINS>(
293-
self,
294-
_pins: PINS,
295-
config: CONFIG,
296-
clocks: &CoreClocks,
297-
prec: rec::Qspi,
298-
) -> Qspi<stm32::QUADSPI>
299-
where
300-
CONFIG: Into<Config>,
301-
PINS: PinsBank2,
302-
{
303-
Qspi::qspi_unchecked(self, config, Bank::Two, clocks, prec)
304-
}
305-
306-
fn qspi_unchecked<CONFIG>(
307-
self,
308-
config: CONFIG,
189+
config: impl Into<Config>,
309190
bank: Bank,
310191
clocks: &CoreClocks,
311192
prec: rec::Qspi,
312-
) -> Qspi<stm32::QUADSPI>
313-
where
314-
CONFIG: Into<Config>,
315-
{
316-
Qspi::qspi_unchecked(self, config, bank, clocks, prec)
193+
) -> Qspi<stm32::QUADSPI> {
194+
Qspi::new_unchecked(self, config, bank, clocks, prec)
317195
}
318196
}

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