Merge pull request #68 from stm32-rs/revert-gpio-fix-travis-bump-stm32

Fix and bump build. Fix travis too.

Author: MabezDev

.travis.yml

@@ -15,6 +15,6 @@ matrix:
   fast_finish: true
 
 install:
-  - rustup target add thumbv7em-none-eabihf
+  - rustup target add thumbv7em-none-eabi
 
 script: tools/check.py $COMMAND

Cargo.toml

@@ -23,7 +23,7 @@ edition = "2018"
 [dependencies]
 cortex-m = "0.5.8"
 nb = "0.1.1"
-stm32l4 = "0.7.0"
+stm32l4 = "0.8.0"
 as-slice = "0.1"
 
 [dependencies.cast]

src/gpio.rs

@@ -553,41 +553,3 @@ gpio!(GPIOC, gpioc, gpioc, gpiocen, gpiocrst, PCx, [
     PC14: (pc14, 14, Input<Floating>, AFRH),
     PC15: (pc15, 15, Input<Floating>, AFRH),
 ]);
-
-gpio!(GPIOD, gpiod, gpiod, gpioden, gpiodrst, PDx, [
-    PD0: (pd0, 0, Input<Floating>, AFRL),
-    PD1: (pd1, 1, Input<Floating>, AFRL),
-    PD2: (pd2, 2, Input<Floating>, AFRL),
-    PD3: (pd3, 3, Input<Floating>, AFRL),
-    PD4: (pd4, 4, Input<Floating>, AFRL),
-    PD5: (pd5, 5, Input<Floating>, AFRL),
-    PD6: (pd6, 6, Input<Floating>, AFRL),
-    PD7: (pd7, 7, Input<Floating>, AFRL),
-    PD8: (pd8, 8, Input<Floating>, AFRH),
-    PD9: (pd9, 9, Input<Floating>, AFRH),
-    PD10: (pd10, 10, Input<Floating>, AFRH),
-    PD11: (pd11, 11, Input<Floating>, AFRH),
-    PD12: (pd12, 12, Input<Floating>, AFRH),
-    PD13: (pd13, 13, Input<Floating>, AFRH),
-    PD14: (pd14, 14, Input<Floating>, AFRH),
-    PD15: (pd15, 15, Input<Floating>, AFRH),
-]);
-
-gpio!(GPIOE, gpioe, gpioe, gpioeen, gpioerst, PEx, [
-    PE0: (pe0, 0, Input<Floating>, AFRL),
-    PE1: (pe1, 1, Input<Floating>, AFRL),
-    PE2: (pe2, 2, Input<Floating>, AFRL),
-    PE3: (pe3, 3, Input<Floating>, AFRL),
-    PE4: (pe4, 4, Input<Floating>, AFRL),
-    PE5: (pe5, 5, Input<Floating>, AFRL),
-    PE6: (pe6, 6, Input<Floating>, AFRL),
-    PE7: (pe7, 7, Input<Floating>, AFRL),
-    PE8: (pe8, 8, Input<Floating>, AFRH),
-    PE9: (pe9, 9, Input<Floating>, AFRH),
-    PE10: (pe10, 10, Input<Floating>, AFRH),
-    PE11: (pe11, 11, Input<Floating>, AFRH),
-    PE12: (pe12, 12, Input<Floating>, AFRH),
-    PE13: (pe13, 13, Input<Floating>, AFRH),
-    PE14: (pe14, 14, Input<Floating>, AFRH),
-    PE15: (pe15, 15, Input<Floating>, AFRH),
-]);

src/pwm.rs

@@ -141,35 +141,31 @@ macro_rules! hal {
                 apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
 
                 if PINS::C1 {
-                    tim.ccmr1_output
-                        .modify(|_, w| unsafe { w.oc1pe().set_bit().oc1m().bits(6) });
+                    tim.ccmr1_output().modify(|_, w| unsafe { w.oc1pe().set_bit().oc1m().bits(6) });
                 }
 
                 if PINS::C2 {
-                    tim.ccmr1_output
-                        .modify(|_, w| unsafe { w.oc2pe().set_bit().oc2m().bits(6) });
+                    tim.ccmr1_output().modify(|_, w| unsafe { w.oc2pe().set_bit().oc2m().bits(6) });
                 }
 
                 if PINS::C3 {
-                    tim.ccmr2_output
-                        .modify(|_, w| unsafe { w.oc3pe().set_bit().oc3m().bits(6) });
+                    tim.ccmr2_output().modify(|_, w| unsafe { w.oc3pe().set_bit().oc3m().bits(6) });
                 }
 
                 if PINS::C4 {
-                    tim.ccmr2_output
-                        .modify(|_, w| unsafe { w.oc4pe().set_bit().oc4m().bits(6) });
+                    tim.ccmr2_output().modify(|_, w| unsafe { w.oc4pe().set_bit().oc4m().bits(6) });
                 }
                 let clk = clocks.pclk1().0;
                 let freq = freq.0;
                 let ticks = clk / freq;
 
                 // maybe this is all u32? also, why no `- 1` vs `timer.rs`?
                 let psc = u16(ticks / (1 << 16)).unwrap();
-                tim.psc.write(|w| unsafe { w.psc().bits(psc) });
+                tim.psc.write(|w| { w.psc().bits(psc) });
                 let arr = u16(ticks / u32(psc + 1)).unwrap();
                 tim.arr.write(|w| { w.arr().bits(u32(arr)) });
 
-                tim.cr1.write(|w| unsafe {
+                tim.cr1.write(|w| {
                     w.cms()
                         .bits(0b00)
                         .dir().clear_bit()

src/rtc.rs

@@ -213,7 +213,7 @@ fn byte_to_bcd2(byte: u8) -> (u8, u8){
     (bcd_high, ((bcd_high << 4) | value) as u8)
 }
 
-fn bcd2_to_byte(bcd: (u8, u8)) -> u8 { // TODO fix this
+fn bcd2_to_byte(bcd: (u8, u8)) -> u8 {
     let value = bcd.1 | bcd.0 << 4;
 
     let tmp = ((value & 0xF0) >> 0x4) * 10;

src/serial.rs

@@ -15,7 +15,6 @@ use crate::stm32::{USART1, USART2};
 use void::Void;
 
 use crate::gpio::gpioa::{PA10, PA2, PA3, PA9};
-use crate::gpio::gpiod::{PD5, PD6};
 use crate::gpio::gpiob::{PB6, PB7};
 use crate::gpio::{AF7, Alternate, Input, Floating};
 use crate::rcc::{APB1R1, APB2, Clocks};
@@ -63,10 +62,6 @@ impl Pins<USART2> for (PA2<Alternate<AF7, Input<Floating>>>, PA3<Alternate<AF7,
     const REMAP: u8 = 0;
 }
 
-impl Pins<USART2> for (PD5<Alternate<AF7, Input<Floating>>>, PD6<Alternate<AF7, Input<Floating>>>) {
-    const REMAP: u8 = 0;
-}
-
 
 /// Serial abstraction
 pub struct Serial<USART, PINS> {

src/spi.rs

@@ -4,7 +4,6 @@ use core::ptr;
 
 use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
 use nb;
-use crate::stm32::{SPI1, /* TODO SPI2, */ SPI3};
 
 use crate::gpio::gpioa::{PA5, PA6, PA7};
 use crate::gpio::{AF5, Input, Floating, Alternate};
@@ -178,8 +177,50 @@ macro_rules! hal {
     }
 }
 
+
+use crate::stm32::SPI1;
+#[cfg(any(
+    feature = "stm32l4x1",
+    feature = "stm32l4x2",
+    feature = "stm32l4x3",
+    feature = "stm32l4x5",
+    feature = "stm32l4x6"
+))]
 hal! {
     SPI1: (spi1, APB2, spi1en, spi1rst, pclk2),
-    // SPI2: (spi2, APB1R1, spi2en, spi2rst, pclk1), // NOT Avail on 32k(b|c)
+}
+
+
+#[cfg(any(
+    feature = "stm32l4x1",
+    feature = "stm32l4x2",
+    feature = "stm32l4x5",
+    feature = "stm32l4x6",
+))]
+use crate::stm32::SPI3;
+
+#[cfg(any(
+    feature = "stm32l4x1",
+    feature = "stm32l4x2",
+    feature = "stm32l4x5",
+    feature = "stm32l4x6",
+))]
+hal! {
     SPI3: (spi3, APB1R1, spi3en, spi3rst, pclk1),
 }
+
+#[cfg(any(
+    feature = "stm32l4x3",
+    feature = "stm32l4x5",
+    feature = "stm32l4x6",
+))]
+use crate::stm32::SPI2;
+
+#[cfg(any(
+    feature = "stm32l4x3",
+    feature = "stm32l4x5",
+    feature = "stm32l4x6",
+))]
+hal! {
+    SPI2: (spi2, APB1R1, spi2en, spi2rst, pclk1),
+}

tools/check.py

@@ -30,7 +30,8 @@ def main():
 
     features = ["{},rt".format(x)
             for x in crate_info["features"].keys()
-            if x != "rt"]
+            if x != "rt"
+            if x != "unproven"]
 
     if 'size_check' in sys.argv:
         cargo_cmd = ['cargo', 'build', '--release']