Experimental support for Synopsys USB library.

The STM32L4 series are available in different lines:
  - STM32L4x1: Access Line.
  - STM32L4x2: USB Device.
  - STM32L4x3: USB Device, LCD.
  - STM32L4x5: USB OTG 2.0.
  - STM32L4x6: USB OTG 2.0, LCD.

USB OTG is implemented by the Synopsys USB library, which is also
used by a number of products in their STM32F-series chips.

This commit adds support for full-speed (FS) USB support for the
4x5 and 4x6 lines.

Author: Pål-Kristian Engstad

Cargo.toml

@@ -50,6 +50,11 @@ version = "0.5.0"
 features = ["ram_access_2x16"]
 optional = true
 
+[dependencies.synopsys-usb-otg]
+version = "0.2.4"
+features = ["cortex-m", "fs"]
+optional = true
+
 [package.metadata.docs.rs]
 features = ["rt", "stm32l4x2", "stm32-usbd"]
 
@@ -61,6 +66,7 @@ stm32l4x3 = ["stm32l4/stm32l4x3"]
 stm32l4x5 = ["stm32l4/stm32l4x5"]
 stm32l4x6 = ["stm32l4/stm32l4x6"]
 unproven = ["embedded-hal/unproven"]
+otg_fs = ["synopsys-usb-otg"]
 
 [dev-dependencies]
 panic-halt = "0.2.0"

src/lib.rs

@@ -117,6 +117,10 @@ pub mod gpio;
     feature = "stm32l4x6"
 ))]
 pub mod i2c;
+#[cfg(all(feature = "otg_fs",
+          any(feature = "stm32l4x5", feature = "stm32l4x6")
+))]
+pub mod otg_fs;
 #[cfg(any(
     feature = "stm32l4x1",
     feature = "stm32l4x2",

src/otg_fs.rs

@@ -0,0 +1,54 @@
+//! USB OTG full-speed peripheral
+//!
+//! The STM32L4 series only supports the full-speed peripheral.
+
+use crate::stm32;
+
+use crate::gpio::{
+    gpioa::{PA11, PA12},
+    Alternate, Floating, Input, AF10,
+};
+use crate::time::Hertz;
+
+pub use synopsys_usb_otg::UsbBus;
+use synopsys_usb_otg::UsbPeripheral;
+
+pub struct USB {
+    pub usb_global: stm32::OTG_FS_GLOBAL,
+    pub usb_device: stm32::OTG_FS_DEVICE,
+    pub usb_pwrclk: stm32::OTG_FS_PWRCLK,
+    pub pin_dm: PA11<Alternate<AF10, Input<Floating>>>,
+    pub pin_dp: PA12<Alternate<AF10, Input<Floating>>>,
+    pub hclk: Hertz,
+}
+
+unsafe impl Sync for USB {}
+
+unsafe impl UsbPeripheral for USB {
+    const REGISTERS: *const () = stm32::OTG_FS_GLOBAL::ptr() as *const ();
+
+    const HIGH_SPEED: bool = false;
+    const FIFO_DEPTH_WORDS: usize = 320;
+
+    const ENDPOINT_COUNT: usize = 6;
+
+    fn enable() {
+        let rcc = unsafe { &*stm32::RCC::ptr() };
+
+        cortex_m::interrupt::free(|_| {
+            // Enable USB peripheral
+            rcc.ahb2enr.modify(|_, w| w.otgfsen().set_bit());
+            let _ = rcc.ahb2enr.read().otgfsen().bit_is_set();
+
+            // Reset USB peripheral
+            rcc.ahb2rstr.modify(|_, w| w.otgfsrst().set_bit());
+            rcc.ahb2rstr.modify(|_, w| w.otgfsrst().clear_bit());
+        });
+    }
+
+    fn ahb_frequency_hz(&self) -> u32 {
+        self.hclk.0
+    }
+}
+
+pub type UsbBusType = UsbBus<USB>;

src/rcc.rs

@@ -778,8 +778,7 @@ impl CFGR {
 
         // MSI always starts on reset
         if self.msi.is_none() {
-            rcc.cr
-                .modify(|_, w| w.msion().clear_bit().msipllen().clear_bit())
+            rcc.cr.modify(|_, w| w.msion().clear_bit().msipllen().clear_bit())
         }
 
         //