We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 3b076a6 commit 266e62fCopy full SHA for 266e62f
src/rcc.rs
@@ -684,12 +684,16 @@ impl CFGR {
684
// adjust flash wait states
685
unsafe {
686
acr.acr().write(|w| {
687
- w.latency().bits(if sysclk <= 24_000_000 {
+ w.latency().bits(if hclk <= 16_000_000 {
688
0b000
689
- } else if sysclk <= 48_000_000 {
+ } else if hclk <= 32_000_000 {
690
0b001
691
- } else {
+ } else if hclk <= 48_000_000 {
692
0b010
693
+ } else if hclk <= 64_000_000 {
694
+ 0b011
695
+ } else {
696
+ 0b100
697
})
698
699
}
0 commit comments