Merge pull request #15 from MabezDev/tsc-configuration

RCC/TSC:

Author: MabezDev

.vscode/launch.json

@@ -13,7 +13,7 @@
             "debugger_args": [
                 "-nx" // dont use the .gdbinit file
             ],
-            "executable": "./target/thumbv7em-none-eabi/debug/examples/touch",
+            "executable": "./target/thumbv7em-none-eabi/debug/examples/serial",
             "remote": true,
             "target": ":3333",
             "cwd": "${workspaceRoot}",
@@ -34,7 +34,7 @@
             "debugger_args": [
                 "-nx" // dont use the .gdbinit file
             ],
-            "executable": "./target/thumbv7em-none-eabi/release/examples/touch",
+            "executable": "./target/thumbv7em-none-eabi/release/examples/serial",
             "remote": true,
             "target": ":3333",
             "cwd": "${workspaceRoot}",

Cargo.toml

@@ -17,7 +17,6 @@ exclude = [
 [dependencies]
 cortex-m = "0.5.2"
 nb = "0.1.1"
-cortex-m-rt = "0.5.1"
 
 [dependencies.cast]
 version  = "0.2.2"
@@ -38,6 +37,7 @@ features = ["stm32l4x2", "rt"]
 [dev-dependencies]
 panic-semihosting = "0.3.0"
 cortex-m-semihosting = "0.3.0"
+cortex-m-rt = "0.5.1"
 
 [profile.dev]
 incremental = false

examples/serial.rs

@@ -34,9 +34,9 @@ fn main() -> ! {
     // let mut gpiob = p.GPIOB.split(&mut rcc.ahb2);
 
     // clock configuration using the default settings (all clocks run at 8 MHz)
-    let clocks = rcc.cfgr.freeze(&mut flash.acr);
+    // let clocks = rcc.cfgr.freeze(&mut flash.acr);
     // TRY this alternate clock configuration (clocks run at nearly the maximum frequency)
-    // let clocks = rcc.cfgr.sysclk(64.mhz()).pclk1(32.mhz()).freeze(&mut flash.acr);
+    let clocks = rcc.cfgr.sysclk(80.mhz()).pclk1(80.mhz()).pclk2(80.mhz()).freeze(&mut flash.acr);
 
     // The Serial API is highly generic
     // TRY the commented out, different pin configurations

examples/touch.rs

@@ -44,7 +44,7 @@ fn main() -> ! {
     // let mut c3 = gpiob.pb7.into_touch_channel(&mut gpiob.moder, &mut gpiob.otyper, &mut gpiob.afrl);
 
     // , (c1, c2, c3) 
-    let tsc = Tsc::tsc(p.TSC, sample_pin, &mut rcc.ahb1);
+    let tsc = Tsc::tsc(p.TSC, sample_pin, &mut rcc.ahb1, None);
 
     let baseline = tsc.acquire(&mut c1).unwrap();
     let threshold = (baseline / 100) * 60;

src/rcc.rs

@@ -351,10 +351,10 @@ impl CFGR {
             .modify(|_, w| unsafe { 
                 w.pllsrc()
                     .bits(pllsrc_bits)
-                    .pllm().bits(pllmul_bits)
+                    .pllm().bits(0b0) // no division, how to calculate?
+                    .pllr().bits(0b0) // no division, how to calculate?
+                    .plln().bits(pllmul_bits)
             });
-            // .plln().bits(n) // TODO?
-            // .pllr().bits(r)
 
             rcc.cr.modify(|_, w| w.pllon().set_bit());
 

src/tsc.rs

@@ -76,33 +76,67 @@ pub struct Tsc<SPIN> {
     tsc: TSC
 }
 
+pub struct Config {
+    pub clock_prescale: Option<ClockPrescaler>,
+    pub max_count_error: Option<MaxCountError>,
+}
+
+pub enum ClockPrescaler {
+    Hclk = 0b000,
+    HclkDiv2 = 0b001,
+    HclkDiv4 = 0b010,
+    HclkDiv8 = 0b011,
+    HclkDiv16 = 0b100,
+    HclkDiv32 = 0b101,
+    HclkDiv64 = 0b110,
+    HclkDiv128 = 0b111,
+}
+
+pub enum MaxCountError {
+    /// 000: 255
+    U255 = 000,
+    /// 001: 511
+    U511 = 001,
+    /// 010: 1023
+    U1023 = 010,
+    /// 011: 2047
+    U2047 = 011,
+    /// 100: 4095
+    U4095 = 100,
+    /// 101: 8191
+    U8191 = 101,
+    /// 110: 16383
+    U16383 = 110
+}
+
 impl<SPIN> Tsc<SPIN> {
-    pub fn tsc(tsc: TSC, sample_pin: SPIN, ahb: &mut AHB1) -> Self
+    pub fn tsc(tsc: TSC, sample_pin: SPIN, ahb: &mut AHB1, cfg: Option<Config>) -> Self
         where SPIN: SamplePin<TSC>
     {
         /* Enable the peripheral clock */
         ahb.enr().modify(|_, w| w.tscen().set_bit());
         ahb.rstr().modify(|_, w| w.tscrst().set_bit());
         ahb.rstr().modify(|_, w| w.tscrst().clear_bit());
 
+        let config = cfg.unwrap_or(Config {
+            clock_prescale: None,
+            max_count_error: None
+        });
+
         tsc.cr.write(|w| unsafe {
             w.ctph()
                 .bits((1 << 28) as u8)
                 .ctpl()
                 .bits((1 << 24) as u8)
+                // TODO configure sse?
                 .sse()
-                .clear_bit()
+                .set_bit()
+                .ssd()
+                .bits(16)
                 .pgpsc()
-                .bits((2 << 12) as u8)
+                .bits(config.clock_prescale.unwrap_or(ClockPrescaler::Hclk) as u8)
                 .mcv()
-                // 000: 255
-                // 001: 511
-                // 010: 1023
-                // 011: 2047
-                // 100: 4095
-                // 101: 8191
-                // 110: 16383
-                .bits(0b101) // TODO make this value configurable
+                .bits(config.max_count_error.unwrap_or(MaxCountError::U8191) as u8)
                 .tsce()
                 .set_bit()
         });