Merge pull request #228 from akloboucnik/lptimer-irq-fix

Fix LPTIMx configuration on start

Author: korken89

Cargo.toml

@@ -139,3 +139,6 @@ required-features = ["rt", "stm32l4x6", "otg_fs"]
 name = "i2c_write"
 required-features = ["stm32l4x1"]
 
+[[example]]
+name = "lptim_rtic"
+required-features = ["rt", "stm32l4x2"]

examples/lptim_rtic.rs

@@ -0,0 +1,99 @@
+//! Test with
+//! cargo flash --release --features stm32l4x2,rt --chip STM32L452RETx --example lptim_rtic --target thumbv7em-none-eabi
+//! on Nucleo-L452-P board
+#![deny(unsafe_code)]
+#![no_main]
+#![no_std]
+extern crate panic_rtt_target;
+
+use rtt_target::rprintln;
+use stm32l4xx_hal::{
+    flash::ACR,
+    gpio::{gpiob::PB13, Output, PushPull, State},
+    lptimer::{ClockSource, Event, LowPowerTimer, LowPowerTimerConfig, PreScaler},
+    pac::LPTIM1,
+    prelude::*,
+    pwr::Pwr,
+    rcc::{ClockSecuritySystem, Clocks, CrystalBypass, RccExt, CFGR},
+    time::U32Ext,
+};
+
+// this is the LD4 on Nucleo-L452-P
+type Led = PB13<Output<PushPull>>;
+type Timer = LowPowerTimer<LPTIM1>;
+
+pub fn configure_clock_tree(cfgr: CFGR, acr: &mut ACR, pwr: &mut Pwr) -> Clocks {
+    cfgr.lse(CrystalBypass::Disable, ClockSecuritySystem::Disable)
+        .sysclk(80.mhz())
+        .freeze(acr, pwr)
+}
+
+#[rtic::app(device = stm32l4xx_hal::pac, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        led: Led,
+        lptim: Timer,
+    }
+
+    #[init]
+    fn init(ctx: init::Context) -> init::LateResources {
+        rtt_target::rtt_init_print!();
+
+        rprintln!("Init start");
+        let device = ctx.device;
+        // Configure the clock.
+        let mut rcc = device.RCC.constrain();
+        let mut flash = device.FLASH.constrain();
+        let mut pwr = device.PWR.constrain(&mut rcc.apb1r1);
+        let mut gpiob = device.GPIOB.split(&mut rcc.ahb2);
+        let clocks = configure_clock_tree(rcc.cfgr, &mut flash.acr, &mut pwr);
+
+        // PB13 is a user led on Nucleo-L452-P board
+        let led = gpiob.pb13.into_push_pull_output_with_state(
+            &mut gpiob.moder,
+            &mut gpiob.otyper,
+            State::Low,
+        );
+        rprintln!("Clocks = {:#?}", clocks);
+        let lptim_config = LowPowerTimerConfig::default()
+            .clock_source(ClockSource::LSE)
+            .prescaler(PreScaler::U1)
+            .arr_value(32_768u16); // roughly 1s
+        let mut lptim = LowPowerTimer::lptim1(
+            device.LPTIM1,
+            lptim_config,
+            &mut rcc.apb1r1,
+            &mut rcc.ccipr,
+            clocks,
+        );
+        lptim.listen(Event::AutoReloadMatch);
+        init::LateResources { lptim, led }
+    }
+
+    #[task(binds = LPTIM1, resources = [lptim, led])]
+    fn timer_tick(mut ctx: timer_tick::Context) {
+        let timer_tick::Resources { lptim, led } = ctx.resources;
+        if lptim.is_event_triggered(Event::AutoReloadMatch) {
+            lptim.clear_event_flag(Event::AutoReloadMatch);
+            rprintln!("LPTIM1 tick");
+
+            if led.is_set_high().unwrap() {
+                led.set_low().unwrap();
+            } else {
+                led.set_high().unwrap();
+            }
+        }
+    }
+
+    #[idle]
+    fn idle(_ctx: idle::Context) -> ! {
+        loop {
+            // See https://github.com/probe-rs/probe-rs/issues/350
+            core::hint::spin_loop();
+        }
+    }
+
+    extern "C" {
+        fn LCD();
+    }
+};

src/lptimer.rs

@@ -201,17 +201,9 @@ macro_rules! hal {
 
                 instance.enable();
 
-                // Write compare, arr, and continous mode start register _after_ enabling lptim
                 instance.start_continuous_mode();
-
-                // This operation is sound as arr_value is a u16, and there are 16 writeable bits
-                instance
-                    .lptim
-                    .arr
-                    .write(|w| unsafe { w.bits(arr_value as u32) });
-
+                instance.set_autoreload(arr_value);
                 instance.set_compare_match(compare_value);
-
                 instance
             }
 
@@ -264,9 +256,36 @@ macro_rules! hal {
             /// Set the compare match field for this LowPowerTimer
             #[inline]
             pub fn set_compare_match(&mut self, value: u16) {
+                // clear compare register update ok flag
+                self.lptim.icr.write(|w| w.cmpokcf().set_bit());
+
                 // This operation is sound as compare_value is a u16, and there are 16 writeable bits
                 // Additionally, the LPTIM peripheral will always be in the enabled state when this code is called
                 self.lptim.cmp.write(|w| unsafe { w.bits(value as u32) });
+
+                // wait for compare register update ok interrupt to be signalled
+                // (see RM0394 Rev 4, sec 30.4.10 for further explanation and
+                // sec. 30.7.1, Bit 4 for register field description)
+                while self.lptim.isr.read().cmpok().bit_is_clear() {}
+            }
+
+            /// Set auto reload register
+            /// has to be used _after_ enabling of lptim
+            #[inline(always)]
+            pub fn set_autoreload(&mut self, arr_value: u16) {
+                // clear autoreload register OK interrupt flag
+                self.lptim.icr.write(|w| w.arrokcf().set_bit());
+
+                // Write autoreload value
+                // This operation is sound as arr_value is a u16, and there are 16 writeable bits
+                self.lptim
+                    .arr
+                    .write(|w| unsafe { w.bits(arr_value as u32) });
+
+                // wait for autoreload write ok interrupt to be signalled
+                // (see RM0394 Rev 4, sec 30.4.10 for further explanation and
+                // sec. 30.7.1, Bit 4 for register field description)
+                while self.lptim.isr.read().arrok().bit_is_clear() {}
             }
 
             /// Get the current counter value for this LowPowerTimer