Skip to content

Commit 3e4b51f

Browse files
committed
Reworked PWR to use a constrain trait.
1 parent 69aaa71 commit 3e4b51f

File tree

3 files changed

+16
-14
lines changed

3 files changed

+16
-14
lines changed

examples/rtc.rs

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ use hal::stm32l4::stm32l4x2;
1919

2020
use hal::delay::Delay;
2121
use hal::rtc::Rtc;
22-
use hal::pwr::Pwr;
2322
use hal::datetime::{Date,Time};
2423
use rt::ExceptionFrame;
2524

@@ -42,12 +41,9 @@ fn main() -> ! {
4241

4342
// Try a different clock configuration
4443
let clocks = rcc.cfgr.freeze(&mut flash.acr);
45-
// let clocks = rcc.cfgr
46-
// .sysclk(64.mhz())
47-
// .pclk1(32.mhz())
48-
// .freeze(&mut flash.acr);
44+
4945
let mut timer = Delay::new(cp.SYST, clocks);
50-
let mut pwr = Pwr::pwr(&mut rcc.apb1r1);
46+
let mut pwr = dp.PWR.constrain(&mut rcc.apb1r1);
5147
let rtc = Rtc::rtc(dp.RTC, &mut rcc.apb1r1, &mut rcc.bdcr, &mut pwr.cr1);
5248

5349
let mut time = Time::new(21.hours(), 57.minutes(), 32.seconds(), false);
@@ -64,6 +60,8 @@ fn main() -> ! {
6460
date = rtc.get_date();
6561

6662

63+
writeln!(hstdout, "Time: {:?}", time).unwrap();
64+
writeln!(hstdout, "Date: {:?}", date).unwrap();
6765
writeln!(hstdout, "Good bye!").unwrap();
6866
loop {}
6967
}

src/prelude.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,4 +6,5 @@ pub use gpio::GpioExt as _GpioExtHal;
66
pub use hal::prelude::*; // embedded hal traits
77
pub use time::U32Ext as _stm32f30x_hal_time_U32Ext;
88
pub use datetime::U32Ext as _stm32f30x_hal_datetime;
9-
pub use dma::DmaExt as _DmaExtHal;
9+
pub use dma::DmaExt as _DmaExtHal;
10+
pub use pwr::PwrExt as _PwrExtHal;

src/pwr.rs

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,3 @@
1-
// TODO impl power module so we enable backup domain for rtc etc
2-
// apb1r1.enr().modify(|_, w| w.pwren().set_bit());
3-
41
use rcc::{APB1R1};
52
use stm32l4::stm32l4x2::{pwr, PWR};
63

@@ -12,11 +9,17 @@ pub struct Pwr {
129
pub cr4: CR4,
1310
}
1411

15-
impl Pwr {
16-
pub fn pwr(apb1r1: &mut APB1R1) -> Self {
17-
apb1r1.enr().modify(|_, w| w.pwren().set_bit());
12+
/// Extension trait that constrains the `PWR` peripheral
13+
pub trait PwrExt {
14+
/// Constrains the `PWR` peripheral so it plays nicely with the other abstractions
15+
fn constrain(self, &mut APB1R1) -> Pwr;
16+
}
1817

19-
Self {
18+
impl PwrExt for PWR {
19+
fn constrain(self, apb1r1: &mut APB1R1) -> Pwr {
20+
// Enable the peripheral clock
21+
apb1r1.enr().modify(|_, w| w.pwren().set_bit());
22+
Pwr {
2023
cr1: CR1 { _0: () },
2124
cr2: CR2 { _0: () },
2225
cr3: CR3 { _0: () },

0 commit comments

Comments
 (0)