Added PWR module for power control. This was required for RTC. The RTC now 'works' but I think the date formatting is wrong, I set a time of 19 hours and when I get time its 7 (12h difference).

Author: MabezDev

examples/rtc.rs

@@ -20,6 +20,7 @@ use hal::stm32l4::stm32l4x2;
 use hal::delay::Delay;
 use hal::rtc::Rtc;
 use hal::rtc::Time;
+use hal::pwr::Pwr;
 use hal::datetime::*;
 use rt::ExceptionFrame;
 
@@ -47,8 +48,8 @@ fn main() -> ! {
     //     .pclk1(32.mhz())
     //     .freeze(&mut flash.acr);
     let mut timer = Delay::new(cp.SYST, clocks);
-
-    let rtc = Rtc::init(dp.RTC, &mut rcc.bdcr);
+    let mut pwr = Pwr::pwr(&mut rcc.apb1r1);
+    let rtc = Rtc::rtc(dp.RTC, &mut rcc.apb1r1, &mut rcc.bdcr, &mut pwr.cr1);
     let time = Time::new(0, 0, 19, false);
     rtc.set_time(&time);
 

src/lib.rs

@@ -24,6 +24,7 @@ pub mod timer;
 pub mod spi;
 pub mod datetime;
 pub mod rtc;
+pub mod pwr;
 
 
 #[cfg(test)]

src/pwr.rs

@@ -0,0 +1,79 @@
+// TODO impl power module so we enable backup domain for rtc etc
+// apb1r1.enr().modify(|_, w| w.pwren().set_bit());
+
+use rcc::{APB1R1};
+use stm32l4::stm32l4x2::{pwr, PWR};
+
+
+pub struct Pwr {
+    pub cr1: CR1,
+    pub cr2: CR2,
+    pub cr3: CR3,
+    pub cr4: CR4,
+}
+
+impl Pwr {
+    pub fn pwr(apb1r1: &mut APB1R1) -> Self {
+        apb1r1.enr().modify(|_, w| w.pwren().set_bit());
+
+        Self {
+            cr1: CR1 { _0: () },
+            cr2: CR2 { _0: () },
+            cr3: CR3 { _0: () },
+            cr4: CR4 { _0: () },
+        }
+    }
+}
+
+/// CR1
+pub struct CR1 {
+    _0: (),
+}
+
+impl CR1 {
+    // TODO remove `allow`
+    #[allow(dead_code)]
+    pub(crate) fn reg(&mut self) -> &pwr::CR1 {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*PWR::ptr()).cr1 }
+    }
+}
+/// CR2
+pub struct CR2 {
+    _0: (),
+}
+
+impl CR2 {
+    // TODO remove `allow`
+    #[allow(dead_code)]
+    pub(crate) fn reg(&mut self) -> &pwr::CR2 {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*PWR::ptr()).cr2 }
+    }
+}
+/// CR3
+pub struct CR3 {
+    _0: (),
+}
+
+impl CR3 {
+    // TODO remove `allow`
+    #[allow(dead_code)]
+    pub(crate) fn reg(&mut self) -> &pwr::CR3 {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*PWR::ptr()).cr3 }
+    }
+}
+/// CR4
+pub struct CR4 {
+    _0: (),
+}
+
+impl CR4 {
+    // TODO remove `allow`
+    #[allow(dead_code)]
+    pub(crate) fn reg(&mut self) -> &pwr::CR4 {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*PWR::ptr()).cr4 }
+    }
+}

src/rcc.rs

@@ -24,6 +24,7 @@ impl RccExt for RCC {
             apb1r2: APB1R2 { _0: () },
             apb2: APB2 { _0: () },
             bdcr: BDCR { _0: () },
+            csr: CSR { _0: () },
             cfgr: CFGR {
                 hclk: None,
                 pclk1: None,
@@ -48,12 +49,29 @@ pub struct Rcc {
     pub apb1r2: APB1R2,
     /// Advanced Peripheral Bus 2 (APB2) registers
     pub apb2: APB2,
+    /// Clock configuration register
     pub cfgr: CFGR,
     /// Backup domain control register
-    pub bdcr : BDCR,
+    pub bdcr: BDCR,
+    /// Control/Status Register
+    pub csr: CSR, 
 }
 
-// AMBA High-performance Bus (AHB1) registers
+// CSR Control/Status Register
+pub struct CSR {
+    _0: (),
+}
+
+impl CSR {
+    // TODO remove `allow`
+    #[allow(dead_code)]
+    pub(crate) fn csr(&mut self) -> &rcc::CSR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).csr }
+    }
+}
+
+// BDCR Backup domain control register registers
 pub struct BDCR {
     _0: (),
 }
@@ -377,6 +395,13 @@ impl CFGR {
 
         while rcc.cfgr.read().sws().bits() != sysclk_src_bits {}
 
+        // Turn on the internal 32khz lsi oscillator
+        rcc.csr.modify(|_, w| {
+            w.lsion().set_bit()
+        });
+        // Wait until LSI is running
+        while rcc.csr.read().lsirdy().bit_is_clear() {}
+
 
         Clocks {
             hclk: Hertz(hclk),

src/rtc.rs

@@ -1,7 +1,8 @@
 /// RTC peripheral abstraction
 
 use datetime::*;
-use rcc::{BDCR};
+use rcc::{BDCR, APB1R1};
+use pwr;
 use stm32l4::stm32l4x2::{RTC};
 
 #[derive(Clone,Copy,Debug)]
@@ -29,7 +30,16 @@ pub struct Rtc {
 }
 
 impl Rtc {
-    pub fn init(rtc: RTC, bdcr: &mut BDCR) -> Self {
+    pub fn rtc(rtc: RTC, apb1r1: &mut APB1R1, bdcr: &mut BDCR, pwrcr1: &mut pwr::CR1) -> Self {
+        // enable peripheral clock for communication
+        apb1r1.enr().modify(|_, w| w.rtcapben().set_bit());
+        pwrcr1.reg().read(); // read to allow the pwr clock to enable
+        
+        pwrcr1.reg().modify(|_, w| w.dbp().set_bit());
+        while pwrcr1.reg().read().dbp().bit_is_clear() {}
+        
+        bdcr.enr().modify(|_, w| { w.bdrst().set_bit() }); // reset
+        
         bdcr.enr().modify(|_, w| unsafe {
             w.rtcsel()
                 /* 
@@ -41,8 +51,11 @@ impl Rtc {
                 .bits(0b10)
                 .rtcen()
                 .set_bit()
+                .bdrst() // reset required for clock source change
+                .clear_bit()
         });
 
+
        write_protection(&rtc, false);
         {
             init_mode(&rtc, true);
@@ -151,8 +164,9 @@ fn write_protection(rtc: &RTC, enable: bool){
 fn init_mode(rtc: &RTC, enabled: bool) {
     if enabled {
         let isr = rtc.isr.read();
-        if isr.initf().bit_is_clear() {
-            rtc.isr.write(|w| unsafe { w.bits(0xFFFFFFFF) }); // Sets init mode
+        if isr.initf().bit_is_clear() { // are we already in init mode?
+            rtc.isr.write(|w| { w.init().set_bit() });
+            // rtc.isr.write(|w| unsafe { w.bits(0xFFFFFFFF) }); // Sets init mode
             while rtc.isr.read().initf().bit_is_clear() {} // wait to return to init state
         } 
     } else {