Merge pull request #121 from Fabien-B/serial_half_duplex

Adds Half-Duplex capability to Serial.

Author: korken89

examples/serial_half_duplex.rs

@@ -0,0 +1,87 @@
+//! Test the serial interface in Half-Duplex mode.
+//!
+//! This example requires you to hook-up a pullup resistor on the TX pin. RX pin is not used.
+//! Resistor value depends on the baurate and line caracteristics, 1KOhms works well in most cases.
+//! Half-Duplex mode internally connect TX to RX, meaning that bytes sent will also be received.
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate cortex_m;
+#[macro_use(entry, exception)]
+extern crate cortex_m_rt as rt;
+#[macro_use(block)]
+extern crate nb;
+extern crate panic_semihosting;
+
+extern crate stm32l4xx_hal as hal;
+// #[macro_use(block)]
+// extern crate nb;
+
+use crate::hal::prelude::*;
+use crate::hal::serial::{Config, Serial};
+use crate::rt::ExceptionFrame;
+use cortex_m::asm;
+
+#[entry]
+fn main() -> ! {
+    let p = hal::stm32::Peripherals::take().unwrap();
+
+    let mut flash = p.FLASH.constrain();
+    let mut rcc = p.RCC.constrain();
+    let mut pwr = p.PWR.constrain(&mut rcc.apb1r1);
+
+    let mut gpioa = p.GPIOA.split(&mut rcc.ahb2);
+    // let mut gpiob = p.GPIOB.split(&mut rcc.ahb2);
+
+    // clock configuration using the default settings (all clocks run at 8 MHz)
+    // let clocks = rcc.cfgr.freeze(&mut flash.acr);
+    // TRY this alternate clock configuration (clocks run at nearly the maximum frequency)
+    let clocks = rcc
+        .cfgr
+        .sysclk(80.mhz())
+        .pclk1(80.mhz())
+        .pclk2(80.mhz())
+        .freeze(&mut flash.acr, &mut pwr);
+
+    // The Serial API is highly generic
+    // TRY the commented out, different pin configurations
+    // let tx = gpioa.pa9.into_af7(&mut gpioa.moder, &mut gpioa.afrh).set_open_drain();
+    let tx = gpioa
+        .pa2
+        .into_af7(&mut gpioa.moder, &mut gpioa.afrl)
+        .set_open_drain();
+    // let tx = gpiob.pb6.into_af7(&mut gpiob.moder, &mut gpiob.afrl).set_open_drain();
+
+    // TRY using a different USART peripheral here
+    let serial = Serial::usart2(
+        p.USART2,
+        (tx,),
+        Config::default().baudrate(9_600.bps()),
+        clocks,
+        &mut rcc.apb1r1,
+    );
+    let (mut tx, mut rx) = serial.split();
+
+    let sent = b'X';
+
+    // The `block!` macro makes an operation block until it finishes
+    // NOTE the error type is `!`
+
+    block!(tx.write(sent)).ok();
+
+    let received = block!(rx.read()).unwrap();
+
+    assert_eq!(received, sent);
+
+    // if all goes well you should reach this breakpoint
+    asm::bkpt();
+
+    loop {}
+}
+
+#[exception]
+fn HardFault(ef: &ExceptionFrame) -> ! {
+    panic!("{:#?}", ef);
+}

src/serial.rs

@@ -15,7 +15,7 @@ use stable_deref_trait::StableDeref;
 use crate::hal::serial::{self, Write};
 
 use crate::dma::{dma1, CircBuffer, DMAFrame, FrameReader, FrameSender};
-use crate::gpio::{self, Alternate, Floating, Input};
+use crate::gpio::{self, Alternate, AlternateOD, Floating, Input};
 use crate::pac;
 use crate::rcc::{Clocks, APB1R1, APB2};
 use crate::time::{Bps, U32Ext};
@@ -289,6 +289,11 @@ macro_rules! hal {
                             w.ovrdis().set_bit();
                         }
 
+                        // configure Half Duplex
+                        if PINS::HALF_DUPLEX {
+                            w.hdsel().set_bit();
+                        }
+
                         w
                     });
 
@@ -777,6 +782,9 @@ where
 /// Marks pins as being as being TX pins for the given USART instance
 pub trait TxPin<Instance>: private::SealedTx {}
 
+/// Marks pins as being TX Half Duplex pins for the given USART instance
+pub trait TxHalfDuplexPin<Instance>: private::SealedTxHalfDuplex {}
+
 /// Marks pins as being as being RX pins for the given USART instance
 pub trait RxPin<Instance>: private::SealedRx {}
 
@@ -810,6 +818,13 @@ macro_rules! impl_pin_traits {
                         gpio::$tx<Alternate<gpio::$af, Input<Floating>>> {}
                 )*
 
+                $(
+                    impl private::SealedTxHalfDuplex for
+                        gpio::$tx<AlternateOD<gpio::$af, Input<Floating>>> {}
+                    impl TxHalfDuplexPin<pac::$instance> for
+                        gpio::$tx<AlternateOD<gpio::$af, Input<Floating>>> {}
+                )*
+
                 $(
                     impl private::SealedRx for
                         gpio::$rx<Alternate<gpio::$af, Input<Floating>>> {}
@@ -901,6 +916,7 @@ impl_pin_traits! {
 pub trait Pins<USART> {
     const FLOWCTL: bool;
     const DEM: bool;
+    const HALF_DUPLEX: bool;
 }
 
 // No flow control, just Rx+Tx
@@ -911,6 +927,17 @@ where
 {
     const FLOWCTL: bool = false;
     const DEM: bool = false;
+    const HALF_DUPLEX: bool = false;
+}
+
+// No flow control Half_duplex, just Tx
+impl<Instance, Tx> Pins<Instance> for (Tx,)
+where
+    Tx: TxHalfDuplexPin<Instance>,
+{
+    const FLOWCTL: bool = false;
+    const DEM: bool = false;
+    const HALF_DUPLEX: bool = true;
 }
 
 // Hardware flow control, Rx+Tx+Rts+Cts
@@ -923,6 +950,7 @@ where
 {
     const FLOWCTL: bool = true;
     const DEM: bool = false;
+    const HALF_DUPLEX: bool = false;
 }
 
 // DEM for RS485 mode
@@ -934,11 +962,13 @@ where
 {
     const FLOWCTL: bool = false;
     const DEM: bool = true;
+    const HALF_DUPLEX: bool = false;
 }
 
 /// Contains supertraits used to restrict which traits users can implement
 mod private {
     pub trait SealedTx {}
+    pub trait SealedTxHalfDuplex {}
     pub trait SealedRx {}
     pub trait SealedRtsDe {}
     pub trait SealedCts {}