Merge pull request #30 from mathk/master

* Adds GPIOE support
* Added MSI clock support.

Author: MabezDev

Cargo.toml

@@ -23,7 +23,7 @@ edition = "2018"
 [dependencies]
 cortex-m = "0.5.8"
 nb = "0.1.1"
-stm32l4 = "0.5.0"
+stm32l4 = "0.6.0"
 as-slice = "0.1"
 
 [dependencies.cast]
@@ -52,6 +52,7 @@ stm32l4x2 = ["stm32l4/stm32l4x2"]
 stm32l4x3 = ["stm32l4/stm32l4x3"]
 stm32l4x5 = ["stm32l4/stm32l4x5"]
 stm32l4x6 = ["stm32l4/stm32l4x6"]
+stm32l47x = ["stm32l4x6"]
 unproven = ["embedded-hal/unproven"]
 
 [dev-dependencies]

examples/serial_vcom.rs

@@ -27,23 +27,26 @@ fn main() -> ! {
 
     let mut flash = p.FLASH.constrain();
     let mut rcc = p.RCC.constrain();
-    let mut gpioa = p.GPIOA.split(&mut rcc.ahb2);
+    // let mut gpioa = p.GPIOA.split(&mut rcc.ahb2);
     // let mut gpiob = p.GPIOB.split(&mut rcc.ahb2);
+    let mut gpiod = p.GPIOD.split(&mut rcc.ahb2);
 
     // clock configuration using the default settings (all clocks run at 8 MHz)
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
     // TRY this alternate clock configuration (clocks run at nearly the maximum frequency)
     // let clocks = rcc.cfgr.sysclk(64.mhz()).pclk1(32.mhz()).freeze(&mut flash.acr);
 
-    let tx = gpioa.pa2.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
-     // let tx = gpiob.pb6.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
+    //let tx = gpioa.pa2.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
+    // let tx = gpiob.pb6.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
+    let tx = gpiod.pd5.into_af7(&mut gpiod.moder, &mut gpiod.afrl);
 
-    let rx = gpioa.pa3.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
-     // let rx = gpiob.pb7.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
+    // let rx = gpioa.pa3.into_af7(&mut gpioa.moder, &mut gpioa.afrl);
+    // let rx = gpiob.pb7.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
+    let rx = gpiod.pd6.into_af7(&mut gpiod.moder, &mut gpiod.afrl);
 
      // TRY using a different USART peripheral here
-    let serial = Serial::usart2(p.USART2, (tx, rx), 9_600.bps(), clocks, &mut rcc.apb1r1);
-    let (mut tx, _) = serial.split();
+    let serial = Serial::usart2(p.USART2, (tx, rx), 115_200.bps(), clocks, &mut rcc.apb1r1);
+    let (mut tx, mut rx) = serial.split();
 
     let sent = b'X';
 
@@ -58,10 +61,11 @@ fn main() -> ! {
     block!(tx.write(sent)).ok();
     block!(tx.write(sent)).ok();
 
-    // when using virtual com port for recieve, causes a framing error
-    // let received = block!(rx.read()).unwrap();
+    // when using virtual com port for recieve can causes a framing error
+    // On the stm32l476 discovery it is working fine at 115200 baud
+    let received = block!(rx.read()).unwrap();
 
-    // assert_eq!(received, sent);
+    assert_eq!(received, sent);
 
     // if all goes well you should reach this breakpoint
     asm::bkpt();

src/gpio.rs

@@ -587,8 +587,23 @@ gpio!(GPIOB, gpiob, gpiob, gpioben, gpiobrst, PBx, [
     PB5: (pb5, 5, Input<Floating>, AFRL),
     PB6: (pb6, 6, Input<Floating>, AFRL),
     PB7: (pb7, 7, Input<Floating>, AFRL),
+    PB8: (pb8, 8, Input<Floating>, AFRH),
+    PB9: (pb9, 9, Input<Floating>, AFRH),
+    PB10: (pb10, 10, Input<Floating>, AFRH),
+    PB11: (pb11, 11, Input<Floating>, AFRH),
 ]);
 
+gpio!(GPIOD, gpiod, gpioc, gpioden, gpiodrst, PDx, [
+    PD0: (pd0, 0, Input<Floating>, AFRL),
+    PD1: (pd1, 1, Input<Floating>, AFRL),
+    PD2: (pd2, 2, Input<Floating>, AFRL),
+    PD3: (pd3, 3, Input<Floating>, AFRL),
+    PD4: (pd4, 4, Input<Floating>, AFRL),
+    PD5: (pd5, 5, Input<Floating>, AFRL),
+    PD6: (pd6, 6, Input<Floating>, AFRL),
+    PD7: (pd7, 7, Input<Floating>, AFRL),
+    PD8: (pd8, 8, Input<Floating>, AFRH),
+]);
 
 gpio!(GPIOE, gpioe, gpioc, gpioeen, gpioerst, PEx, [
     PE0: (pe0, 0, Input<Floating>, AFRL),
@@ -599,5 +614,5 @@ gpio!(GPIOE, gpioe, gpioc, gpioeen, gpioerst, PEx, [
     PE5: (pe5, 5, Input<Floating>, AFRL),
     PE6: (pe6, 6, Input<Floating>, AFRL),
     PE7: (pe7, 7, Input<Floating>, AFRL),
-    PE8: (pe8, 8, Input<Floating>, AFRL),
+    PE8: (pe8, 8, Input<Floating>, AFRH),
 ]);

src/i2c.rs

@@ -4,7 +4,7 @@ use cast::u8;
 use crate::stm32::{I2C1, I2C2};
 
 use crate::gpio::gpioa::{PA10, PA9};
-use crate::gpio::gpiob::{PB6, PB7};
+use crate::gpio::gpiob::{PB6, PB7, PB10, PB11};
 use crate::gpio::{AF4, Alternate, OpenDrain, Output};
 use crate::hal::blocking::i2c::{Write, WriteRead, Read};
 use crate::rcc::{APB1R1, Clocks};
@@ -39,6 +39,8 @@ unsafe impl SclPin<I2C1> for PA9<Alternate<AF4, Output<OpenDrain>>> {}
 unsafe impl SdaPin<I2C1> for PA10<Alternate<AF4, Output<OpenDrain>>> {}
 unsafe impl SclPin<I2C1> for PB6<Alternate<AF4, Output<OpenDrain>>> {}
 unsafe impl SdaPin<I2C1> for PB7<Alternate<AF4, Output<OpenDrain>>> {}
+unsafe impl SclPin<I2C2> for PB10<Alternate<AF4, Output<OpenDrain>>> {}
+unsafe impl SdaPin<I2C2> for PB11<Alternate<AF4, Output<OpenDrain>>> {}
 
 /// I2C peripheral operating in master mode
 pub struct I2c<I2C, PINS> {
@@ -56,7 +58,7 @@ macro_rules! busy_wait {
             } else if isr.arlo().bit_is_set() {
                 return Err(Error::Arbitration);
             } else if isr.nackf().bit_is_set() {
-                return Err(Error::Nack);  
+                return Err(Error::Nack);
             } else if isr.$flag().bit_is_set() {
                 break;
             } else {
@@ -313,4 +315,4 @@ macro_rules! hal {
 hal! {
     I2C1: (i2c1, i2c1en, i2c1rst),
     I2C2: (i2c2, i2c2en, i2c2rst),
-}
+}

src/rcc.rs

@@ -8,13 +8,42 @@ use crate::stm32::{rcc, RCC};
 use crate::flash::ACR;
 use crate::time::Hertz;
 
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum MsiFreq {
+    #[doc = "range 0 around 100 kHz"]
+    RANGE100K = 0,
+    #[doc = "range 1 around 200 kHz"]
+    RANGE200K = 1,
+    #[doc = "range 2 around 400 kHz"]
+    RANGE400K = 2,
+    #[doc = "range 3 around 800 kHz"]
+    RANGE800K = 3,
+    #[doc = "range 4 around 1 MHz"]
+    RANGE1M = 4,
+    #[doc = "range 5 around 2 MHz"]
+    RANGE2M = 5,
+    #[doc = "range 6 around 4 MHz"]
+    RANGE4M = 6,
+    #[doc = "range 7 around 8 MHz"]
+    RANGE8M = 7,
+    #[doc = "range 8 around 16 MHz"]
+    RANGE16M = 8,
+    #[doc = "range 9 around 24 MHz"]
+    RANGE24M = 9,
+    #[doc = "range 10 around 32 MHz"]
+    RANGE32M = 10,
+    #[doc = "range 11 around 48 MHz"]
+    RANGE48M = 11,
+}
+
 /// Extension trait that constrains the `RCC` peripheral
 pub trait RccExt {
     /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions
     fn constrain(self) -> Rcc;
 }
 
 impl RccExt for RCC {
+
     fn constrain(self) -> Rcc {
         Rcc {
             ahb1: AHB1 { _0: () },
@@ -25,10 +54,13 @@ impl RccExt for RCC {
             apb2: APB2 { _0: () },
             bdcr: BDCR { _0: () },
             csr: CSR { _0: () },
+            #[cfg(not(feature = "stm32l47x"))]
             crrcr: CRRCR { _0: () },
             cfgr: CFGR {
                 hclk: None,
+                #[cfg(not(feature = "stm32l47x"))]
                 hsi48: false,
+                msi: None,
                 lsi: false,
                 pclk1: None,
                 pclk2: None,
@@ -60,6 +92,7 @@ pub struct Rcc {
     /// Control/Status Register
     pub csr: CSR,
     /// Clock recovery RC register
+    #[cfg(not(feature = "stm32l47x"))]
     pub crrcr: CRRCR,
 }
 
@@ -78,17 +111,20 @@ impl CSR {
 }
 
 /// Clock recovery RC register
+#[cfg(not(feature = "stm32l47x"))]
 pub struct CRRCR {
     _0: (),
 }
 
+#[cfg(not(feature = "stm32l47x"))]
 impl CRRCR {
     // TODO remove `allow`
     #[allow(dead_code)]
     pub(crate) fn crrcr(&mut self) -> &rcc::CRRCR {
         // NOTE(unsafe) this proxy grants exclusive access to this register
         unsafe { &(*RCC::ptr()).crrcr }
     }
+
     pub fn is_hsi48_on(&mut self) -> bool {
         self.crrcr().read().hsi48on().bit()
     }
@@ -228,7 +264,9 @@ const HSI: u32 = 16_000_000; // Hz
 pub struct CFGR {
     hclk: Option<u32>,
     // should we use an option? it can really only be on/off
+    #[cfg(not(feature = "stm32l47x"))]
     hsi48: bool,
+    msi: Option<MsiFreq>,
     lsi: bool,
     pclk1: Option<u32>,
     pclk2: Option<u32>,
@@ -246,13 +284,20 @@ impl CFGR {
         self
     }
 
-    /// Sets HSI48 clock on or off (the default)
+    /// Enable the 48Mh USB, RNG, SDMMC clock source.
+    #[cfg(not(feature = "stm32l47x"))]
     pub fn hsi48(mut self, on: bool) -> Self
     {
         self.hsi48 = on;
         self
     }
 
+    pub fn msi(mut self, range: MsiFreq) -> Self
+    {
+        self.msi = Some(range);
+        self
+    }
+
     /// Sets LSI clock on (the default) or off
     pub fn lsi(mut self, on: bool) -> Self
     {
@@ -298,7 +343,7 @@ impl CFGR {
     }
 
     /// Freezes the clock configuration, making it effective
-    pub fn freeze(self, acr: &mut ACR) -> Clocks {
+    pub fn common_freeze(&self, acr: &mut ACR) -> (Hertz, Hertz, Hertz, u8, u8, Hertz){
 
         let pllconf = if self.pllcfg.is_none() {
             let plln = (2 * self.sysclk.unwrap_or(HSI)) / HSI;
@@ -456,27 +501,73 @@ impl CFGR {
             while rcc.csr.read().lsirdy().bit_is_clear() {}
         }
 
-        // Turn on HSI48 if required
-        if self.hsi48 {
+        if let Some(msi) = self.msi {
+            unsafe { rcc.cr.modify(|_, w| w.msirange().bits(msi as u8).msirgsel().set_bit().msion().set_bit() )};
+            // Wait until MSI is running
+            while rcc.cr.read().msirdy().bit_is_clear() {}
+        }
+
+        (Hertz(hclk), Hertz(pclk1), Hertz(pclk2), ppre1, ppre2, Hertz(sysclk))
+    }
+
+
+    #[cfg(not(feature = "stm32l47x"))]
+    pub fn freeze(self, acr: &mut ACR) -> Clocks {
+
+        let (hclk, pclk1, pclk2, ppre1, ppre2, sysclk) = self.common_freeze(acr);
+        let mut usb_rng = false;
+
+        let rcc = unsafe { &*RCC::ptr() };
+        // Turn on USB, RNG Clock using the HSI48CLK source (default)
+        if !cfg!(feature = "stm32l47x") && self.hsi48 {
             // p. 180 in ref-manual
             rcc.crrcr.modify(|_, w| w.hsi48on().set_bit());
             // Wait until HSI48 is running
             while rcc.crrcr.read().hsi48rdy().bit_is_clear() {}
+            usb_rng = true;
         }
 
+        Clocks {
+            hclk,
+            lsi: self.lsi,
+            hsi48: self.hsi48,
+            usb_rng,
+            msi: self.msi,
+            pclk1,
+            pclk2,
+            ppre1,
+            ppre2,
+            sysclk,
+        }
+    }
+
+    #[cfg(feature = "stm32l47x")]
+    pub fn freeze(self, acr: &mut ACR) -> Clocks {
 
+        let (hclk, pclk1, pclk2, ppre1, ppre2, sysclk) = self.common_freeze(acr);
+
+        let mut usb_rng = false;
+
+        let rcc = unsafe { &*RCC::ptr() };
+        // Select MSI as clock source for usb48, rng ...
+        if let Some(MsiFreq::RANGE48M) = self.msi {
+            unsafe { rcc.ccipr.modify(|_, w| w.clk48sel().bits(0b11)) };
+            usb_rng = true;
+        }
 
         Clocks {
-            hclk: Hertz(hclk),
-            hsi48: self.hsi48,
+            hclk,
             lsi: self.lsi,
-            pclk1: Hertz(pclk1),
-            pclk2: Hertz(pclk2),
+            usb_rng,
+            msi: self.msi,
+            pclk1,
+            pclk2,
             ppre1,
             ppre2,
-            sysclk: Hertz(sysclk),
+            sysclk,
         }
     }
+
 }
 
 #[derive(Clone, Copy)]
@@ -496,7 +587,10 @@ pub struct PllConfig {
 #[derive(Clone, Copy, Debug)]
 pub struct Clocks {
     hclk: Hertz,
+    #[cfg(not(feature = "stm32l47x"))]
     hsi48: bool,
+    usb_rng: bool,
+    msi: Option<MsiFreq>,
     lsi: bool,
     pclk1: Hertz,
     pclk2: Hertz,
@@ -514,10 +608,16 @@ impl Clocks {
     }
 
     /// Returns status of HSI48
+    #[cfg(not(feature = "stm32l47x"))]
     pub fn hsi48(&self) -> bool {
         self.hsi48
     }
 
+    /// Returns if usb rng clock is available
+    pub fn usb_rng(&self) -> bool {
+        self.usb_rng
+    }
+
     /// Returns status of HSI48
     pub fn lsi(&self) -> bool {
         self.lsi

src/rng.rs

@@ -21,7 +21,7 @@ impl RngExt for RNG {
 
         // hsi48 should be turned on previously
         // TODO: should we return a Result instead of asserting here?
-        assert!(clocks.hsi48());
+        assert!(clocks.usb_rng());
 
         ahb2.enr().modify(|_, w| w.rngen().set_bit());
         // if we don't do this... we can be "too fast", and