@@ -8,7 +8,7 @@ use crate::stm32::{TIM1, TIM15, TIM2};
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use crate :: gpio:: gpioa:: { PA0 , PA1 , PA10 , PA11 , PA2 , PA3 , PA8 , PA9 } ;
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use crate :: gpio:: gpiob:: PB14 ;
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- use crate :: gpio:: { Alternate , AlternateOD , Floating , Input , Output , PushPull , AF1 } ;
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+ use crate :: gpio:: { Alternate , AlternateOD , Floating , Input , Output , PushPull , AF1 , AF14 } ;
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use crate :: rcc:: { Clocks , APB1R1 , APB2 } ;
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use crate :: time:: Hertz ;
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@@ -23,17 +23,17 @@ pub trait Pins<TIM> {
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}
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macro_rules! pins_to_channels_mapping {
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- ( $( $TIMX: ident: ( $( $PINX: ident) ,+ ) , ( $( $ENCHX: ident) ,* ) ; ) + ) => {
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+ ( $( $TIMX: ident: ( $( $PINX: ident) ,+ ) , ( $( $ENCHX: ident) ,+ ) , ( $ ( $AF : ident ) ,+ ) ; ) + ) => {
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$(
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#[ allow( unused_parens) ]
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- impl Pins <$TIMX> for ( $( $PINX<Alternate <AF1 , Output <PushPull >>>) ,+)
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+ impl Pins <$TIMX> for ( $( $PINX<Alternate <$AF , Output <PushPull >>>) ,+)
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{
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$( const $ENCHX: bool = true ; ) +
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type Channels = ( $( Pwm <$TIMX, $ENCHX>) ,+) ;
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}
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#[ allow( unused_parens) ]
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- impl Pins <$TIMX> for ( $( $PINX<AlternateOD <AF1 , Input <Floating >>>) ,+)
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+ impl Pins <$TIMX> for ( $( $PINX<AlternateOD <$AF , Input <Floating >>>) ,+)
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{
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$( const $ENCHX: bool = true ; ) +
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type Channels = ( $( Pwm <$TIMX, $ENCHX>) ,+) ;
@@ -44,41 +44,48 @@ macro_rules! pins_to_channels_mapping {
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pins_to_channels_mapping ! {
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// TIM1
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- TIM1 : ( PA8 , PA9 , PA10 , PA11 ) , ( C1 , C2 , C3 , C4 ) ;
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- TIM1 : ( PA9 , PA10 , PA11 ) , ( C2 , C3 , C4 ) ;
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- TIM1 : ( PA8 , PA10 , PA11 ) , ( C1 , C3 , C4 ) ;
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- TIM1 : ( PA8 , PA9 , PA11 ) , ( C1 , C2 , C4 ) ;
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- TIM1 : ( PA8 , PA9 , PA10 ) , ( C1 , C2 , C3 ) ;
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- TIM1 : ( PA10 , PA11 ) , ( C3 , C4 ) ;
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- TIM1 : ( PA9 , PA11 ) , ( C2 , C4 ) ;
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- TIM1 : ( PA9 , PA10 ) , ( C2 , C3 ) ;
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- TIM1 : ( PA8 , PA11 ) , ( C1 , C4 ) ;
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- TIM1 : ( PA8 , PA10 ) , ( C1 , C3 ) ;
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- TIM1 : ( PA8 , PA9 ) , ( C1 , C2 ) ;
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- TIM1 : ( PA8 ) , ( C1 ) ;
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- TIM1 : ( PA9 ) , ( C2 ) ;
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- TIM1 : ( PA10 ) , ( C3 ) ;
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- TIM1 : ( PA11 ) , ( C4 ) ;
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+ TIM1 : ( PA8 , PA9 , PA10 , PA11 ) , ( C1 , C2 , C3 , C4 ) , ( AF1 , AF1 , AF1 , AF1 ) ;
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+ TIM1 : ( PA9 , PA10 , PA11 ) , ( C2 , C3 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA10 , PA11 ) , ( C1 , C3 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA9 , PA11 ) , ( C1 , C2 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA9 , PA10 ) , ( C1 , C2 , C3 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM1 : ( PA10 , PA11 ) , ( C3 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA9 , PA11 ) , ( C2 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA9 , PA10 ) , ( C2 , C3 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA11 ) , ( C1 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA10 ) , ( C1 , C3 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA8 , PA9 ) , ( C1 , C2 ) , ( AF1 , AF1 ) ;
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+ TIM1 : ( PA8 ) , ( C1 ) , ( AF1 ) ;
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+ TIM1 : ( PA9 ) , ( C2 ) , ( AF1 ) ;
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+ TIM1 : ( PA10 ) , ( C3 ) , ( AF1 ) ;
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+ TIM1 : ( PA11 ) , ( C4 ) , ( AF1 ) ;
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// TIM2
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- TIM2 : ( PA0 , PA1 , PA2 , PA3 ) , ( C1 , C2 , C3 , C4 ) ;
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- TIM2 : ( PA1 , PA2 , PA3 ) , ( C2 , C3 , C4 ) ;
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- TIM2 : ( PA0 , PA2 , PA3 ) , ( C1 , C3 , C4 ) ;
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- TIM2 : ( PA0 , PA1 , PA3 ) , ( C1 , C2 , C4 ) ;
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- TIM2 : ( PA0 , PA1 , PA2 ) , ( C1 , C2 , C3 ) ;
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- TIM2 : ( PA2 , PA3 ) , ( C3 , C4 ) ;
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- TIM2 : ( PA1 , PA3 ) , ( C2 , C4 ) ;
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- TIM2 : ( PA1 , PA2 ) , ( C2 , C3 ) ;
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- TIM2 : ( PA0 , PA3 ) , ( C1 , C4 ) ;
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- TIM2 : ( PA0 , PA2 ) , ( C1 , C3 ) ;
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- TIM2 : ( PA0 , PA1 ) , ( C1 , C2 ) ;
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- TIM2 : ( PA0 ) , ( C1 ) ;
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- TIM2 : ( PA1 ) , ( C2 ) ;
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- TIM2 : ( PA2 ) , ( C3 ) ;
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- TIM2 : ( PA3 ) , ( C4 ) ;
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-
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- // TIM15
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- TIM15 : ( PB14 ) , ( C1 ) ;
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+ TIM2 : ( PA0 , PA1 , PA2 , PA3 ) , ( C1 , C2 , C3 , C4 ) , ( AF1 , AF1 , AF1 , AF1 ) ;
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+ TIM2 : ( PA1 , PA2 , PA3 ) , ( C2 , C3 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA2 , PA3 ) , ( C1 , C3 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA1 , PA3 ) , ( C1 , C2 , C4 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA1 , PA2 ) , ( C1 , C2 , C3 ) , ( AF1 , AF1 , AF1 ) ;
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+ TIM2 : ( PA2 , PA3 ) , ( C3 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA1 , PA3 ) , ( C2 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA1 , PA2 ) , ( C2 , C3 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA3 ) , ( C1 , C4 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA2 ) , ( C1 , C3 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA0 , PA1 ) , ( C1 , C2 ) , ( AF1 , AF1 ) ;
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+ TIM2 : ( PA0 ) , ( C1 ) , ( AF1 ) ;
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+ TIM2 : ( PA1 ) , ( C2 ) , ( AF1 ) ;
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+ TIM2 : ( PA2 ) , ( C3 ) , ( AF1 ) ;
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+ TIM2 : ( PA3 ) , ( C4 ) , ( AF1 ) ;
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+
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+ // TIM15 - TODO: The uncommented lines are awaiting PAC updates to be valid.
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+ TIM15 : ( PB14 ) , ( C1 ) , ( AF14 ) ;
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+ // TIM15: (PB15), (C2), (AF14);
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+ TIM15 : ( PA2 ) , ( C1 ) , ( AF14 ) ;
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+ // TIM15: (PA3), (C2), (AF14);
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+ // TIM15: (PB14, PB15), (C1, C2), (AF14, AF14);
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+ // TIM15: (PB14, PA3), (C1, C2), (AF14, AF14);
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+ // TIM15: (PA2, PB15), (C1, C2), (AF14, AF14);
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+ // TIM15: (PA2, PA3), (C1, C2), (AF14, AF14);
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}
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pub trait PwmExt1 : Sized {
@@ -304,6 +311,11 @@ macro_rules! small_timer {
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tim. ccmr1_output( ) . modify( |_, w| unsafe { w. oc1pe( ) . set_bit( ) . oc1m( ) . bits( 6 ) } ) ;
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}
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+ // TODO: The uncommented lines are awaiting PAC updates to be valid.
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+ // if PINS::C2 {
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+ // tim.ccmr1_output().modify(|_, w| unsafe { w.oc2pe().set_bit().oc2m().bits(6) });
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+ // }
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+
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let clk = clocks. pclk1( ) . 0 ;
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let freq = freq. 0 ;
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let ticks = clk / freq;
@@ -314,6 +326,9 @@ macro_rules! small_timer {
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let arr = ticks / ( psc + 1 ) ;
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unsafe { tim. arr. write( |w| { w. arr( ) . bits( arr as $arr_width) } ) ; }
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+ tim. bdtr. write( |w| w. moe( ) . set_bit( ) ) ;
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+ tim. egr. write( |w| w. ug( ) . set_bit( ) ) ;
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+
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tim. cr1. write( |w| {
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w. opm( ) . clear_bit( )
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. cen( ) . set_bit( )
@@ -325,6 +340,8 @@ macro_rules! small_timer {
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pwm_channels! {
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$TIMX: ( C1 , $arr_width, cc1e, ccr1, ccr1) ,
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+ // TODO: The uncommented line is awaiting PAC updates to be valid.
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+ // (C2, $arr_width, cc2e, ccr2, ccr2),
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}
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) +
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