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Rejig clock checking
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src/rng.rs

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,12 @@ impl RngExt for RNG {
2020
// ...this is now supposed to be done in RCC configuration before freezing
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// hsi48 should be turned on previously or msi at 48mhz
23-
let enabled = {
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clocks.hsi48() ||
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match clocks.msi() {
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Some(msi) => msi == crate::rcc::MsiFreq::RANGE48M,
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None => false,
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}
23+
let msi = match clocks.msi() {
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Some(msi) => msi == crate::rcc::MsiFreq::RANGE48M,
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None => false,
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};
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assert!(enabled);
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let hsi = clocks.hsi48();
28+
assert!(msi || hsi);
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ahb2.enr().modify(|_, w| w.rngen().set_bit());
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// if we don't do this... we can be "too fast", and

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