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stm32-rs: 0.14.0 -> 0.15.1
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21 files changed

+196
-193
lines changed

21 files changed

+196
-193
lines changed

‎CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
1414

1515
## Changed
1616
- `Rtc.alarm_{a,b}` returns `Alarm` instead of `Option<Alarm>`.
17+
- Updated `stm32-rs` from `0.14.0` to `0.15.1`.
1718

1819
### Fixed
1920
- Fixed a documentation bug in `rtc::Alarm`. Values are masked if `true`, but the documentation indicated they are masked if `false`.

‎Cargo.lock

Lines changed: 12 additions & 12 deletions
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‎hal/Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ num-traits = { version = "0.2", default-features = false }
3838
num-integer = { version = "0.1", default-features = false }
3939
paste = "1"
4040
rand_core = "0.6"
41-
stm32wl = { version = "0.14", default-features = false }
41+
stm32wl = { version = "0.15.1", default-features = false }
4242
void = { version = "1", default-features = false }
4343

4444
[dev-dependencies]

‎hal/src/adc.rs

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -149,19 +149,19 @@ pub enum Clk {
149149
impl Clk {
150150
const fn ckmode(&self) -> pac::adc::cfgr2::CKMODE_A {
151151
match self {
152-
Clk::RccHsi | Clk::RccPllP | Clk::RccSysClk => pac::adc::cfgr2::CKMODE_A::ADCLK,
153-
Clk::PClkDiv2 => pac::adc::cfgr2::CKMODE_A::PCLK_DIV2,
154-
Clk::PClkDiv4 => pac::adc::cfgr2::CKMODE_A::PCLK_DIV4,
155-
Clk::PClk => pac::adc::cfgr2::CKMODE_A::PCLK,
152+
Clk::RccHsi | Clk::RccPllP | Clk::RccSysClk => pac::adc::cfgr2::CKMODE_A::Adclk,
153+
Clk::PClkDiv2 => pac::adc::cfgr2::CKMODE_A::PclkDiv2,
154+
Clk::PClkDiv4 => pac::adc::cfgr2::CKMODE_A::PclkDiv4,
155+
Clk::PClk => pac::adc::cfgr2::CKMODE_A::Pclk,
156156
}
157157
}
158158

159159
const fn adcsel(&self) -> pac::rcc::ccipr::ADCSEL_A {
160160
match self {
161-
Clk::RccHsi => pac::rcc::ccipr::ADCSEL_A::HSI16,
162-
Clk::RccPllP => pac::rcc::ccipr::ADCSEL_A::PLLP,
163-
Clk::RccSysClk => pac::rcc::ccipr::ADCSEL_A::SYSCLK,
164-
_ => pac::rcc::ccipr::ADCSEL_A::NOCLOCK,
161+
Clk::RccHsi => pac::rcc::ccipr::ADCSEL_A::Hsi16,
162+
Clk::RccPllP => pac::rcc::ccipr::ADCSEL_A::Pllp,
163+
Clk::RccSysClk => pac::rcc::ccipr::ADCSEL_A::Sysclk,
164+
_ => pac::rcc::ccipr::ADCSEL_A::NoClock,
165165
}
166166
}
167167
}
@@ -579,15 +579,15 @@ impl Adc {
579579
use pac::{adc::cfgr2::CKMODE_A, rcc::ccipr::ADCSEL_A};
580580

581581
match self.adc.cfgr2.read().ckmode().variant() {
582-
CKMODE_A::ADCLK => match rcc.ccipr.read().adcsel().variant() {
583-
ADCSEL_A::NOCLOCK => None,
584-
ADCSEL_A::HSI16 => Some(Clk::RccHsi),
585-
ADCSEL_A::PLLP => Some(Clk::RccPllP),
586-
ADCSEL_A::SYSCLK => Some(Clk::RccSysClk),
582+
CKMODE_A::Adclk => match rcc.ccipr.read().adcsel().variant() {
583+
ADCSEL_A::NoClock => None,
584+
ADCSEL_A::Hsi16 => Some(Clk::RccHsi),
585+
ADCSEL_A::Pllp => Some(Clk::RccPllP),
586+
ADCSEL_A::Sysclk => Some(Clk::RccSysClk),
587587
},
588-
CKMODE_A::PCLK_DIV2 => Some(Clk::PClkDiv2),
589-
CKMODE_A::PCLK_DIV4 => Some(Clk::PClkDiv4),
590-
CKMODE_A::PCLK => Some(Clk::PClk),
588+
CKMODE_A::PclkDiv2 => Some(Clk::PClkDiv2),
589+
CKMODE_A::PclkDiv4 => Some(Clk::PClkDiv4),
590+
CKMODE_A::Pclk => Some(Clk::PClk),
591591
}
592592
}
593593

@@ -656,30 +656,30 @@ impl Adc {
656656
};
657657

658658
let source_freq: Ratio<u32> = match self.adc.cfgr2.read().ckmode().variant() {
659-
CKMODE_A::ADCLK => {
659+
CKMODE_A::Adclk => {
660660
let src: Ratio<u32> = match rcc.ccipr.read().adcsel().variant() {
661-
ADCSEL_A::NOCLOCK => Ratio::new_raw(0, 1),
662-
ADCSEL_A::HSI16 => Ratio::new_raw(16_000_000, 1),
663-
ADCSEL_A::PLLP => crate::rcc::pllpclk(rcc, &rcc.pllcfgr.read()),
664-
ADCSEL_A::SYSCLK => crate::rcc::sysclk(rcc, &rcc.cfgr.read()),
661+
ADCSEL_A::NoClock => Ratio::new_raw(0, 1),
662+
ADCSEL_A::Hsi16 => Ratio::new_raw(16_000_000, 1),
663+
ADCSEL_A::Pllp => crate::rcc::pllpclk(rcc, &rcc.pllcfgr.read()),
664+
ADCSEL_A::Sysclk => crate::rcc::sysclk(rcc, &rcc.cfgr.read()),
665665
};
666666

667667
// only the asynchronous clocks have the prescaler applied
668668
let ccr = self.adc.ccr.read();
669669
let prescaler: u32 = match ccr.presc().variant() {
670670
Some(p) => match p {
671-
PRESC_A::DIV1 => 1,
672-
PRESC_A::DIV2 => 2,
673-
PRESC_A::DIV4 => 4,
674-
PRESC_A::DIV6 => 6,
675-
PRESC_A::DIV8 => 8,
676-
PRESC_A::DIV10 => 10,
677-
PRESC_A::DIV12 => 12,
678-
PRESC_A::DIV16 => 16,
679-
PRESC_A::DIV32 => 32,
680-
PRESC_A::DIV64 => 64,
681-
PRESC_A::DIV128 => 128,
682-
PRESC_A::DIV256 => 256,
671+
PRESC_A::Div1 => 1,
672+
PRESC_A::Div2 => 2,
673+
PRESC_A::Div4 => 4,
674+
PRESC_A::Div6 => 6,
675+
PRESC_A::Div8 => 8,
676+
PRESC_A::Div10 => 10,
677+
PRESC_A::Div12 => 12,
678+
PRESC_A::Div16 => 16,
679+
PRESC_A::Div32 => 32,
680+
PRESC_A::Div64 => 64,
681+
PRESC_A::Div128 => 128,
682+
PRESC_A::Div256 => 256,
683683
},
684684
None => {
685685
error!("Reserved ADC prescaler value {:#X}", ccr.presc().bits());
@@ -689,9 +689,9 @@ impl Adc {
689689

690690
src / prescaler
691691
}
692-
CKMODE_A::PCLK_DIV2 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 2,
693-
CKMODE_A::PCLK_DIV4 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 4,
694-
CKMODE_A::PCLK => crate::rcc::pclk2(rcc, &rcc.cfgr.read()),
692+
CKMODE_A::PclkDiv2 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 2,
693+
CKMODE_A::PclkDiv4 => crate::rcc::pclk2(rcc, &rcc.cfgr.read()) / 4,
694+
CKMODE_A::Pclk => crate::rcc::pclk2(rcc, &rcc.cfgr.read()),
695695
};
696696

697697
source_freq.to_integer()

‎hal/src/aes.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,7 @@ impl Aes {
167167

168168
Aes {
169169
aes,
170-
swap_mode: SwapMode::NONE,
170+
swap_mode: SwapMode::None,
171171
}
172172
}
173173

@@ -275,7 +275,7 @@ impl Aes {
275275
pub const unsafe fn new_no_init(aes: pac::AES) -> Aes {
276276
Aes {
277277
aes,
278-
swap_mode: SwapMode::NONE,
278+
swap_mode: SwapMode::None,
279279
}
280280
}
281281

@@ -316,7 +316,7 @@ impl Aes {
316316
let dp: pac::Peripherals = pac::Peripherals::steal();
317317
Aes {
318318
aes: dp.AES,
319-
swap_mode: SwapMode::NONE,
319+
swap_mode: SwapMode::None,
320320
}
321321
}
322322

@@ -346,7 +346,7 @@ impl Aes {
346346
self.aes.keyr2.write(|w| w.key().bits(key[1]));
347347
self.aes.keyr1.write(|w| w.key().bits(key[2]));
348348
self.aes.keyr0.write(|w| w.key().bits(key[3]));
349-
KeySize::BITS128
349+
KeySize::Bits128
350350
}
351351
8 => {
352352
self.aes.cr.write(|w| w.en().disabled().keysize().bits256());
@@ -358,7 +358,7 @@ impl Aes {
358358
self.aes.keyr2.write(|w| w.key().bits(key[5]));
359359
self.aes.keyr1.write(|w| w.key().bits(key[6]));
360360
self.aes.keyr0.write(|w| w.key().bits(key[7]));
361-
KeySize::BITS256
361+
KeySize::Bits256
362362
}
363363
_ => panic!("Key must be 128-bit or 256-bit not {}-bit", key.len() * 32),
364364
}
@@ -793,7 +793,7 @@ impl Aes {
793793
///
794794
/// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
795795
/// let mut aes: Aes = Aes::new(dp.AES, &mut dp.RCC);
796-
/// let mut rng = Rng::new(dp.RNG, rng::Clk::MSI, &mut dp.RCC);
796+
/// let mut rng = Rng::new(dp.RNG, rng::Clk::Msi, &mut dp.RCC);
797797
///
798798
/// const KEY: [u32; 4] = [0; 4];
799799
///
@@ -840,7 +840,7 @@ impl Aes {
840840
///
841841
/// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
842842
/// let mut aes: Aes = Aes::new(dp.AES, &mut dp.RCC);
843-
/// let mut rng = Rng::new(dp.RNG, rng::Clk::MSI, &mut dp.RCC);
843+
/// let mut rng = Rng::new(dp.RNG, rng::Clk::Msi, &mut dp.RCC);
844844
///
845845
/// const KEY: [u32; 4] = [0; 4];
846846
///

‎hal/src/dac.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,12 @@ pub enum ModePin {
3232
impl From<ModePin> for MODE1_A {
3333
fn from(mp: ModePin) -> Self {
3434
match mp {
35-
ModePin::NormBuf => MODE1_A::NORMALPINBUFFER,
36-
ModePin::NormChipBuf => MODE1_A::NORMALPINCHIPBUFFER,
37-
ModePin::NormNoBuf => MODE1_A::NORMALPINNOBUFFER,
38-
ModePin::SampleHoldBuf => MODE1_A::SHPINBUFFER,
39-
ModePin::SampleHoldChipBuf => MODE1_A::SHPINCHIPBUFFER,
40-
ModePin::SampleHoldNoBuf => MODE1_A::SHPINNOBUFFER,
35+
ModePin::NormBuf => MODE1_A::NormalPinBuffer,
36+
ModePin::NormChipBuf => MODE1_A::NormalPinChipBuffer,
37+
ModePin::NormNoBuf => MODE1_A::NormalPinNoBuffer,
38+
ModePin::SampleHoldBuf => MODE1_A::ShpinBuffer,
39+
ModePin::SampleHoldChipBuf => MODE1_A::ShpinChipBuffer,
40+
ModePin::SampleHoldNoBuf => MODE1_A::ShpinNoBuffer,
4141
}
4242
}
4343
}
@@ -60,8 +60,8 @@ pub enum ModeChip {
6060
impl From<ModeChip> for MODE1_A {
6161
fn from(mc: ModeChip) -> Self {
6262
match mc {
63-
ModeChip::SampleHold => MODE1_A::SHCHIPNOBUFFER,
64-
ModeChip::Norm => MODE1_A::NORMALCHIPNOBUFFER,
63+
ModeChip::SampleHold => MODE1_A::ShchipNoBuffer,
64+
ModeChip::Norm => MODE1_A::NormalChipNoBuffer,
6565
}
6666
}
6767
}

‎hal/src/i2c.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -346,9 +346,9 @@ macro_rules! impl_clocks_reset {
346346
fn clock(rcc: &RCC) -> u32 {
347347
// NOTE(unsafe) atomic read with no side effects
348348
match rcc.ccipr.read().$i2cXsel().variant().unwrap() {
349-
I2C3SEL_A::HSI16 => 16_000_000,
350-
I2C3SEL_A::SYSCLK => sysclk_hz(rcc),
351-
I2C3SEL_A::PCLK => pclk1_hz(rcc),
349+
I2C3SEL_A::Hsi16 => 16_000_000,
350+
I2C3SEL_A::Sysclk => sysclk_hz(rcc),
351+
I2C3SEL_A::Pclk => pclk1_hz(rcc),
352352
}
353353
}
354354
}

‎hal/src/pka.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@ impl Pka {
505505
self.clear_all_flags();
506506
Err(EcdsaSignError::Ram)
507507
} else {
508-
self.start_process(MODE_A::ECDSASIGN);
508+
self.start_process(MODE_A::Ecdsasign);
509509
Ok(())
510510
}
511511
}
@@ -639,7 +639,7 @@ impl Pka {
639639
self.clear_all_flags();
640640
Err(EcdsaVerifyError::Ram)
641641
} else {
642-
self.start_process(MODE_A::ECDSAVERIF);
642+
self.start_process(MODE_A::Ecdsaverif);
643643
Ok(())
644644
}
645645
}

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