Address spelling issues of Available and Tcxo. (#365)

Author: ShakenCodes

.config/lingo.dic

@@ -122,7 +122,6 @@ TCXO
 timestamp
 Timestamp
 tuple
-TXCO
 UART
 UFBGA73
 UFQFPN48

CHANGELOG.md

@@ -6,6 +6,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## [Unreleased]
 ### Changed
+- Renamed function TcxoMode::set_txco_trim() to TcxoMode::set_tcxo_trim() to correct spelling.
+- Renamed enum CmdStatus::Avaliable to CmdStatus::Available to correct spelling.
 - Updated minimum `chrono` version to `0.4.23` to satisfy `cargo-audit`.
 - Changed minimum supported rust version from 1.60 to 1.62.
 

hal/src/adc.rs

@@ -825,7 +825,7 @@ impl Adc {
     /// ```
     #[inline]
     pub fn set_isr(&mut self, isr: u32) {
-        // saftey: reserved bits are masked and will be held at reset value
+        // safety: reserved bits are masked and will be held at reset value
         self.adc.isr.write(|w| unsafe { w.bits(isr & irq::ALL) })
     }
 
@@ -848,7 +848,7 @@ impl Adc {
     /// ```
     #[inline]
     pub fn isr() -> pac::adc::isr::R {
-        // saftey: atomic read with no side-effects
+        // safety: atomic read with no side-effects
         unsafe { (*pac::ADC::PTR).isr.read() }
     }
 
@@ -870,7 +870,7 @@ impl Adc {
     /// ```
     #[inline]
     pub fn set_ier(&mut self, ier: u32) {
-        // saftey: reserved bits are masked and will be held at reset value
+        // safety: reserved bits are masked and will be held at reset value
         self.adc.ier.write(|w| unsafe { w.bits(ier & irq::ALL) })
     }
 
@@ -909,7 +909,7 @@ impl Adc {
     pub fn start_chsel(&mut self, ch: u32) {
         debug_assert!(self.adc.cr.read().adstart().is_not_active());
         // See section 18.3.8 page 542 "Channel selection"
-        // saftey: reserved bits are masked and will be held at reset value
+        // safety: reserved bits are masked and will be held at reset value
         self.adc
             .chselr0()
             .write(|w| unsafe { w.chsel().bits(ch & CH_MASK) });

hal/src/dma/cr.rs

@@ -280,7 +280,7 @@ impl Cr {
     /// ```
     ///
     /// [`enabled`]: crate::dma::Cr::enabled
-    #[must_use = "set_secm returns a modified Cr"]
+    #[must_use = "set_secure returns a modified Cr"]
     pub const fn set_secure(mut self, sec: bool) -> Cr {
         if sec {
             self.val |= 1 << 17;

hal/src/lib.rs

@@ -16,7 +16,7 @@
     all(feature = "stm32wl5x_cm4", feature = "stm32wle5"),
 ))]
 compile_error!(
-    "Multile chip features activated. \
+    "Multiple chip features activated. \
     You must activate exactly one of the following features: \
     stm32wl5x_cm0p, stm32wl5x_cm4, stm32wle5"
 );

hal/src/rtc/mod.rs

@@ -218,14 +218,14 @@ impl Rtc {
     /// Read the RTC status (interrupt) register.
     #[inline]
     pub fn status() -> pac::rtc::sr::R {
-        // saftey: atomic read with no side-effects
+        // safety: atomic read with no side-effects
         unsafe { (*pac::RTC::PTR).sr.read() }
     }
 
     /// Read the RTC masked status (interrupt) register.
     #[inline]
     pub fn masked_status() -> pac::rtc::misr::R {
-        // saftey: atomic read with no side-effects
+        // safety: atomic read with no side-effects
         unsafe { (*pac::RTC::PTR).misr.read() }
     }
 

hal/src/subghz/mod.rs

@@ -188,7 +188,7 @@ pub fn mask_irq() {
 /// details.
 #[inline]
 pub fn rfbusys() -> bool {
-    // safety: atmoic read with no side-effects
+    // safety: atomic read with no side-effects
     unsafe { (*pac::PWR::PTR).sr2.read().rfbusys().is_busy() }
 }
 
@@ -198,7 +198,7 @@ pub fn rfbusys() -> bool {
 /// details.
 #[inline]
 pub fn rfbusyms() -> bool {
-    // saftey: atomic read with no side-effects
+    // safety: atomic read with no side-effects
     unsafe { (*pac::PWR::PTR).sr2.read().rfbusyms().is_busy() }
 }
 
@@ -273,7 +273,7 @@ fn pulse_reset(rcc: &mut pac::RCC) {
 /// const TX_PARAMS: TxParams = TxParams::LP_10.set_ramp_time(RampTime::Micros40);
 ///
 /// const TCXO_MODE: TcxoMode = TcxoMode::new()
-///     .set_txco_trim(TcxoTrim::Volts1pt7)
+///     .set_tcxo_trim(TcxoTrim::Volts1pt7)
 ///     .set_timeout(Timeout::from_millis_sat(10));
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -769,12 +769,12 @@ where
     ///
     /// [`set_rx_duty_cycle`]: crate::subghz::SubGhz::set_rx_duty_cycle
     pub fn set_rtc_period(&mut self, period: Timeout) -> Result<(), Error> {
-        let tobits: u32 = period.into_bits();
+        let to_bits: u32 = period.into_bits();
         self.write(wr_reg![
             RTCPRDR2,
-            (tobits >> 16) as u8,
-            (tobits >> 8) as u8,
-            tobits as u8
+            (to_bits >> 16) as u8,
+            (to_bits >> 8) as u8,
+            to_bits as u8
         ])
     }
 
@@ -907,23 +907,23 @@ where
 
     /// Setup the sub-GHz radio for TX.
     pub fn set_tx(&mut self, timeout: Timeout) -> Result<(), Error> {
-        let tobits: u32 = timeout.into_bits();
+        let to_bits: u32 = timeout.into_bits();
         self.write(&[
             OpCode::SetTx.into(),
-            (tobits >> 16) as u8,
-            (tobits >> 8) as u8,
-            tobits as u8,
+            (to_bits >> 16) as u8,
+            (to_bits >> 8) as u8,
+            to_bits as u8,
         ])
     }
 
     /// Setup the sub-GHz radio for RX.
     pub fn set_rx(&mut self, timeout: Timeout) -> Result<(), Error> {
-        let tobits: u32 = timeout.into_bits();
+        let to_bits: u32 = timeout.into_bits();
         self.write(&[
             OpCode::SetRx.into(),
-            (tobits >> 16) as u8,
-            (tobits >> 8) as u8,
-            tobits as u8,
+            (to_bits >> 16) as u8,
+            (to_bits >> 8) as u8,
+            to_bits as u8,
         ])
     }
 

hal/src/subghz/mod_params.rs

@@ -544,7 +544,7 @@ impl FskModParams {
     ///     .set_bandwidth(FskBandwidth::Bw58)
     ///     .set_fdev(FskFdev::from_hertz(10_000));
     ///
-    /// // 30 PPM is wost case (if the HSE32 crystal meets requirements)
+    /// // 30 PPM is worst case (if the HSE32 crystal meets requirements)
     /// sa::const_assert!(MOD_PARAMS.is_valid(30));
     /// ```
     #[must_use = "the return value indicates if the modulation parameters are valid"]
@@ -851,7 +851,7 @@ impl LoRaModParams {
     /// When possible, enabling the low data rate optimization, relaxes the
     /// total frequency drift over the packet time by 16:
     ///
-    /// Freq_drift_optimise_max = 16 × Freq_drift_max
+    /// Freq_drift_optimize_max = 16 × Freq_drift_max
     ///
     /// # Example
     ///

hal/src/subghz/packet_status.rs

@@ -30,7 +30,7 @@ impl FskPacketStatus {
     /// let pkt_status: FskPacketStatus = FskPacketStatus::from(example_data_from_radio);
     /// let status: Status = pkt_status.status();
     /// assert_eq!(status.mode(), Ok(StatusMode::Rx));
-    /// assert_eq!(status.cmd(), Ok(CmdStatus::Avaliable));
+    /// assert_eq!(status.cmd(), Ok(CmdStatus::Available));
     /// ```
     pub const fn status(&self) -> Status {
         Status::from_raw(self.buf[0])
@@ -195,7 +195,7 @@ impl LoRaPacketStatus {
     /// let pkt_status: LoRaPacketStatus = LoRaPacketStatus::from(example_data_from_radio);
     /// let status: Status = pkt_status.status();
     /// assert_eq!(status.mode(), Ok(StatusMode::Rx));
-    /// assert_eq!(status.cmd(), Ok(CmdStatus::Avaliable));
+    /// assert_eq!(status.cmd(), Ok(CmdStatus::Available));
     /// ```
     pub const fn status(&self) -> Status {
         Status::from_raw(self.buf[0])

hal/src/subghz/stats.rs

@@ -40,7 +40,7 @@ impl<ModType> Stats<ModType> {
     /// let example_data_from_radio: [u8; 7] = [0x54, 0, 0, 0, 0, 0, 0];
     /// let stats: Stats<FskStats> = Stats::from_raw_fsk(example_data_from_radio);
     /// assert_eq!(stats.status().mode(), Ok(StatusMode::Rx));
-    /// assert_eq!(stats.status().cmd(), Ok(CmdStatus::Avaliable));
+    /// assert_eq!(stats.status().cmd(), Ok(CmdStatus::Available));
     /// ```
     pub const fn status(&self) -> Status {
         self.status
@@ -159,7 +159,7 @@ mod test {
         let example_data_from_radio: [u8; 7] = [0x54, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06];
         let stats: Stats<LoRaStats> = Stats::from_raw_lora(example_data_from_radio);
         assert_eq!(stats.status().mode(), Ok(StatusMode::Rx));
-        assert_eq!(stats.status().cmd(), Ok(CmdStatus::Avaliable));
+        assert_eq!(stats.status().cmd(), Ok(CmdStatus::Available));
         assert_eq!(stats.pkt_rx(), 0x0102);
         assert_eq!(stats.pkt_crc(), 0x0304);
         assert_eq!(stats.pkt_hdr_err(), 0x0506);