rtc: add setup_wakeup_timer

Author: newAM

hal/src/rtc.rs

@@ -1,12 +1,13 @@
 //! Real-time clock.
 
 use crate::{pac, rcc::lsi_hz};
-
 use chrono::{Datelike, NaiveDate, NaiveDateTime, NaiveTime, Timelike};
-
-use pac::rcc::{
-    bdcr::RTCSEL_A,
-    csr::LSIPRE_A::{DIV1, DIV128},
+use pac::{
+    rcc::{
+        bdcr::RTCSEL_A,
+        csr::LSIPRE_A::{DIV1, DIV128},
+    },
+    rtc::cr::WUCKSEL_A,
 };
 
 /// RTC clock selection
@@ -22,6 +23,29 @@ pub enum Clk {
     Hse = RTCSEL_A::HSE32 as u8,
 }
 
+/// Status (interrupt) masks.
+///
+/// Used for [`Rtc::clear_status`].
+pub mod stat {
+    /// SSR underflow flag
+    pub const SSRU: u32 = 1 << 6;
+    /// Internal timestamp flag
+    pub const ITS: u32 = 1 << 5;
+    /// Timestamp overflow flag
+    pub const TSOV: u32 = 1 << 4;
+    /// Timestamp flag
+    pub const TS: u32 = 1 << 3;
+    /// Wakeup timer flag
+    pub const WUT: u32 = 1 << 2;
+    /// Alarm B flag
+    pub const ALRB: u32 = 1 << 1;
+    /// Alarm A flag
+    pub const ALRA: u32 = 1 << 0;
+
+    /// All status flags.
+    pub const ALL: u32 = SSRU | ITS | TSOV | TS | WUT | ALRB | ALRA;
+}
+
 /// Real-time clock driver.
 #[derive(Debug)]
 pub struct Rtc {
@@ -183,6 +207,29 @@ impl Rtc {
         }
     }
 
+    /// Read the RTC status (interrupt) register.
+    #[inline]
+    pub fn status() -> pac::rtc::sr::R {
+        // saftey: atomic read with no side-effects
+        unsafe { (*pac::RTC::ptr()).sr.read() }
+    }
+
+    /// Read the RTC masked status (interrupt) register.
+    #[inline]
+    pub fn masked_status() -> pac::rtc::misr::R {
+        // saftey: atomic read with no side-effects
+        unsafe { (*pac::RTC::ptr()).misr.read() }
+    }
+
+    /// Clear status (interrupt) flags.
+    ///
+    /// Status flag masks can be found in [`stat`].
+    #[inline]
+    pub fn clear_status(mask: u32) {
+        // safety: mask is masked with valid register fields
+        unsafe { (*pac::RTC::ptr()).scr.write(|w| w.bits(mask & stat::ALL)) }
+    }
+
     // configure prescaler for a 1Hz clock
     //
     // RM0453 Rev 2 page 996:
@@ -409,6 +456,64 @@ impl Rtc {
         }
     }
 
+    /// Setup the periodic wakeup timer for `sec + 1` seconds.
+    ///
+    /// `sec` can only go up to 2<sup>17</sup> (36 hours), values greater than
+    /// this will be set to the maximum.
+    ///
+    /// # Example
+    ///
+    /// Setup the wakeup timer to go off in 1 hour, without interrupts.
+    ///
+    /// ```no_run
+    /// # use stm32wl_hal::{pac, rtc};
+    /// # let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
+    /// # let mut rtc = rtc::Rtc::new(dp.RTC, rtc::Clk::Lse, &mut dp.PWR, &mut dp.RCC);
+    /// rtc.setup_wakeup_timer(3599, false);
+    /// ```
+    pub fn setup_wakeup_timer(&mut self, sec: u32, irq_en: bool) {
+        // The following sequence is required to configure or change the wakeup
+        // timer auto-reload value (WUT[15:0] in RTC_WUTR):
+
+        // 1. Clear WUTE in RTC_CR to disable the wakeup timer.
+        self.rtc.cr.modify(|_, w| w.wute().clear_bit());
+        // 2. Poll WUTWF until it is set in RTC_ICSR to make sure the access to
+        // wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed.
+        // This step must be skipped in calendar initialization mode.
+        // If WUCKSEL[2] = 0:
+        //  WUTWF is set around 1 ck_wut + 1 RTCCLK cycles after WUTE bit is cleared.
+        // If WUCKSEL[2] = 1:
+        //  WUTWF is set up to 1 ck_apre + 1 RTCCLK cycles after WUTE bit is cleared.
+        while self.rtc.icsr.read().wutwf().bit_is_clear() {}
+        // 3. Program the wakeup auto-reload value WUT[15:0], WUTOCLR[15:0]
+        // and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR).
+        // Set WUTE in RTC_CR to enable the timer again.
+        // The wakeup timer restarts down-counting.
+        // If WUCKSEL[2] = 0:
+        //  WUTWF is cleared around 1 ck_wut + 1 RTCCLK cycles after WUTE bit is set.
+        // If WUCKSEL[2] = 1:
+        //  WUTWF is cleared up to 1 ck_apre + 1 RTCCLK cycles after WUTE bit is set.
+        let (wucksel, sec): (WUCKSEL_A, u16) = match u16::try_from(sec) {
+            Ok(sec) => (WUCKSEL_A::CLOCKSPARE, sec),
+            Err(_) => (
+                WUCKSEL_A::CLOCKSPAREWITHOFFSET,
+                u16::try_from(sec - (1 << 16) - 1).unwrap_or(u16::MAX),
+            ),
+        };
+
+        self.rtc
+            .cr
+            .modify(|_, w| w.wucksel().variant(wucksel).wutie().bit(irq_en));
+        self.rtc.wutr.write(|w| w.wut().bits(sec).wutoclr().bits(0));
+        self.rtc.cr.modify(|_, w| w.wute().set_bit());
+    }
+
+    /// Disable the wakeup timer.
+    #[inline]
+    pub fn disable_wakeup_timer(&mut self) {
+        self.rtc.cr.modify(|_, w| w.wute().clear_bit());
+    }
+
     /// Disable the RTC write protection.
     #[inline]
     pub fn disable_write_protect(&mut self) {

testsuite/src/rtc.rs

@@ -20,7 +20,7 @@ const CYC_PER_MICRO: u32 = FREQ / 1000 / 1000;
 // WARNING will wrap-around eventually, use this for relative timing only
 defmt::timestamp!("{=u32:µs}", DWT::get_cycle_count() / CYC_PER_MICRO);
 
-fn test_set_date_time_with_clk(clk: rtc::Clk) {
+fn test_set_date_time_with_clk(clk: rtc::Clk) -> Rtc {
     let mut dp: pac::Peripherals = unsafe { pac::Peripherals::steal() };
     let mut rtc: Rtc = Rtc::new(dp.RTC, clk, &mut dp.PWR, &mut dp.RCC);
 
@@ -89,6 +89,8 @@ fn test_set_date_time_with_clk(clk: rtc::Clk) {
         after - before
     );
     defmt::assert!(after > before);
+
+    rtc
 }
 
 #[defmt_test::tests]
@@ -126,7 +128,7 @@ mod tests {
         ta.rcc.bdcr.modify(|_, w| w.lseon().on());
         while ta.rcc.bdcr.read().lserdy().is_not_ready() {}
 
-        test_set_date_time_with_clk(rtc::Clk::Lse)
+        test_set_date_time_with_clk(rtc::Clk::Lse);
     }
 
     // must come directly after set_date_time_lse
@@ -152,7 +154,7 @@ mod tests {
     fn set_date_time_lsi(ta: &mut TestArgs) {
         unsafe { pulse_reset_backup_domain(&mut ta.rcc, &mut ta.pwr) };
         unsafe { setup_lsi(&mut ta.rcc, LsiPre::DIV1) };
-        test_set_date_time_with_clk(rtc::Clk::Lsi)
+        test_set_date_time_with_clk(rtc::Clk::Lsi);
     }
 
     #[test]
@@ -162,6 +164,33 @@ mod tests {
             .cr
             .modify(|_, w| w.hseon().enabled().hsebyppwr().vddtcxo());
         while ta.rcc.cr.read().hserdy().is_not_ready() {}
-        test_set_date_time_with_clk(rtc::Clk::Hse)
+        test_set_date_time_with_clk(rtc::Clk::Hse);
+    }
+
+    #[test]
+    fn wakeup_timer(ta: &mut TestArgs) {
+        unsafe { pulse_reset_backup_domain(&mut ta.rcc, &mut ta.pwr) };
+        ta.pwr.cr1.modify(|_, w| w.dbp().enabled());
+        ta.rcc.bdcr.modify(|_, w| w.lseon().on());
+        while ta.rcc.bdcr.read().lserdy().is_not_ready() {}
+        let mut rtc: Rtc = test_set_date_time_with_clk(rtc::Clk::Lse);
+
+        rtc.setup_wakeup_timer(0, false);
+
+        let start: u32 = DWT::get_cycle_count();
+        loop {
+            let elapsed_micros: u32 = DWT::get_cycle_count().wrapping_sub(start) / CYC_PER_MICRO;
+            if Rtc::status().wutf().bit_is_set() {
+                defmt::info!("elapsed: {=u32:µs}", elapsed_micros);
+                // 100ms tolerance
+                defmt::assert!(elapsed_micros > 900_000 && elapsed_micros < 1_100_000);
+                return;
+            } else if elapsed_micros > 3 * 1000 * 1000 {
+                defmt::panic!(
+                    "this is taking too long, elapsed: {=u32:µs}",
+                    elapsed_micros
+                );
+            }
+        }
     }
 }